Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design, for allocating processing functions between a primary processor and a secondary processor is disclosed. A primary processor is provided that performs routine processing duties, including execution of application program code, while the secondary processor is in a sleep state. When the load on the primary processor is deemed to be excessive, the secondary processor is awakened from a sleep state and assigned to perform processing functions that would otherwise need to be performed by the primary processor. If temperatures in the system rise above a threshold, the secondary processor is returned to the sleep state.

Abstract: Systems, methods and media for allocating processing functions between a primary processor and a secondary processor are disclosed. In one embodiment, a primary processor performs routine processing duties, including execution of application program code, while the secondary processor is in a sleep state. When the load on the primary processor is deemed to be excessive, the secondary processor is awakened from a sleep state and assigned to perform processing functions that would otherwise need to be performed by the primary processor. If temperatures in the system rise above a threshold, the secondary processor is returned to the sleep state.

Abstract: An improved solution for authenticating a user seeking to manage a computer system is provided according to aspects of the invention. A user seeking to perform out-of-band management of the computer system can provide a set of credentials to a service processor, which in turn provides them to the computer system for authentication. Additionally, a user seeking to perform in-band management of the computer system can provide a set of credentials to a management agent executing on the computer system for authentication. In either case, the computer system can authenticate the set of credentials, e.g., using an operating system interface.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design, for allocating processing functions between a primary processor and a secondary processor is disclosed. A primary processor is provided that performs routine processing duties, including execution of application program code, while the secondary processor is in a sleep state. When the load on the primary processor is deemed to be excessive, the secondary processor is awakened from a sleep state and assigned to perform processing functions that would otherwise need to be performed by the primary processor. If temperatures in the system rise above a threshold, the secondary processor is returned to the sleep state.

Abstract: An improved solution for authenticating a user seeking to manage a computer system is provided according to aspects of the invention. A user seeking to perform out-of-band management of the computer system can provide a set of credentials to a service processor, which in turn provides them to the computer system for authentication. Additionally, a user seeking to perform in-band management of the computer system can provide a set of credentials to a management agent executing on the computer system for authentication. In either case, the computer system can authenticate the set of credentials, e.g., using an operating system interface.

Abstract: A structure and technique for preventing collisions using a hash table in conjunction with a CAM to identify and prevent collisions of binary keys. A portion of the hash value of a binary key, which does not collide with a portion of the hash value of any other reference binary key, is used as an entry in the hash table. If two or more binary keys have identical values of the portions of the hash values, each of these binary keys are stored in their entirety, in the CAM. The key in the CAM provides a pointer to a data structure where the action associated with that binary key is stored. If the binary key is not found in the CAM, the binary key is hashed, and a specific entry in the hash table is selected using a portion of this hash value.

Abstract: A structure and technique for preventing collisions using a hash table in conjunction with a CAM to identify and prevent collision of binary keys. A portion of the hash value of a binary key, which does not collide with a portion of the hash value of any other reference binary key, is used as an entry in the hash table. If two or more binary keys have identical values of the portions of the hash values, each of these binary keys are stored in their entirety, in the CAM. The key in the CAM provides a pointer to a data structure where the action associated with that binary key is stored. If the binary key is not found in the CAM, the binary key is hashed, and a specific entry in the hash table is selected using a portion of this hash value.

Abstract: Systems, methods and media for allocating processing functions between a primary processor and a secondary processor are disclosed. In one embodiment, a primary processor performs routine processing duties, including execution of application program code, while the secondary processor is in a sleep state. When the load on the primary processor is deemed to be excessive, the secondary processor is awakened from a sleep state and assigned to perform processing functions that would otherwise need to be performed by the primary processor. If temperatures in the system rise above a threshold, the secondary processor is returned to the sleep state.

Abstract: A histogram difference method and system for power/performance measurement and management has low data storage requirements while supporting multiple monitoring applications having different update rates. Histogram data for power usage and/or performance mode is collected at a predetermined rate and the histogram data is read out at periodic intervals by the monitoring applications. The monitoring applications subtract the histogram data from previously read histogram data set to determine a interval difference histogram. The minimum and maximum values for the interval are the lowest-valued and highest-valued bin in the interval difference histogram that have a count greater than zero. The average value for the interval is the mean of the interval difference histogram. A conservative bound of the maximum and minimum values for a system can be determined by adding the values of the maximum and minimum values determined for each subsystem in the system.

Abstract: A histogram difference method and system for power/performance measurement and management has low data storage requirements while supporting multiple monitoring applications having different update rates. Histogram data for power usage and/or performance mode is collected at a predetermined rate and the histogram data is read out at periodic intervals by the monitoring applications. The monitoring applications subtract the histogram data from previously read histogram data set to determine a interval difference histogram. The minimum and maximum values for the interval are the lowest-valued and highest-valued bin in the interval difference histogram that have a count greater than zero. The average value for the interval is the mean of the interval difference histogram. A conservative bound of the maximum and minimum values for a system can be determined by adding the values of the maximum and minimum values determined for each subsystem in the system.

Abstract: A Resource Reservation System includes a Token Generation Unit (TGU) which generates and circulates among nodes of a communications system a Slotted Token (SLT) message having sub-fields to carry identification number for each input port in a node and the resource available for each input port. On receiving the message the Resource Control Unit (RCU) in each node can write port identification number, available resource in appropriate sub-fields of the SLT message, and reserve resources in other nodes by adjusting information in the sub-field associated with the other nodes.

Abstract: A structure and technique for preventing collisions using a hash table in conjunction with a CAM to identify and prevent a collisions of binary keys. A portion of the hash value of a binary key, which does not collide with a portion of the hash value of any other reference binary key, is used as an entry in the hash table. If two or more binary keys have identical values of the portions of the hash values, each of these binary keys are stored in their entirety, in the CAM. The key in the CAM provides a pointer to a data structure where the action associated with that binary key is stored. If the binary key is not found in the CAM, the binary key is hashed, and a specific entry in the hash table is selected using a portion of this hash value.

Abstract: A container has a first and a second opening formed in a lid that releasably closes the container. A first base surrounds the first opening and a second base surrounds the second opening. The narrow end of a retractable, self-deploying funnel engages the first opening and the wide end of a retractable, self-deploying pour spout engages the second opening. Both funnel and pour spout are retracted when the first and second caps engage the first and second bases, respectively. The funnel facilitates charging of a liquid into the container and the pour spout facilitates pouring of a liquid from the container. Each cap includes a vent opening formed in a top wall and a nipple formed in depending relation to an interior surface of the top wall. The nipple plugs the narrow end of the pour spout when the pour spout is in its fully retracted configuration.

Abstract: A funnel assembly includes a collapsible funnel mounted to a base. The funnel is formed by consecutive windings of spring steel wire. Each winding has a reduced diameter so that the windings collectively form a funnel having a conical shape and an inherent bias. The funnel is confined into a relatively small storage space and the funnel is compressed when a cap releasably engages the base. Upon disengaging the cap from the base, the bias unloads and fully deploys the funnel. A downspout depends from the base and engages the fill spout of an oil crankcase so that the funnel assembly is mounted to the fill spout. A user therefore does not hold the funnel assembly while pouring oil from a can into the deployed funnel. By holding the base in one hand and the cap in the other, a user may deploy the funnel and return it to storage without touching the funnel.

Abstract: A network processor utilizes protocol processor units (PPUs) to provide instruction communication for the network. Each PPU includes a core language processor (CLP). Each CLP contains general purpose registers and includes a coprocessor that contains scalar registers and array registers. The CLP controls and instructs a plurality of coprocessors that run in parallel with the CLP. Each coprocessor is a specialized hardware assist engine having direct access to the CLP registers and arrays through two sets of interface signals, a coprocessor execution interface and a coprocessor data interface.

Abstract: A processor adapted for parallel and/or pipelined interconnection with other like processors. An arithmetic logic unit has associated with it an output FIFO register stack having output data lines capable of parallel connection with the output data lines of other such processors, such output stack being loadable with a predetermined neutral value such that when the neutral value is present at their output data lines it permits the data present at the output lines of another such processor connected in parallel therewith to control the output data bus. The invention eliminates the need to have control over several such processors connected in parallel and/or pipelined configuration by way of external arbitration logic.

Abstract: A uniprocessor if formed on plural independently controlled chips each including a primary instruction driven controller and a secondary error driven self-sequencing controller. Each instruction is supplied in parallel to each primary controller which generates an EXIT signal, as it completes execution, to a common external EXIT line. Hardware monitors the local EXIT signal and the common EXIT line state and activates the secondary controller, when a mismatch is detected, to set an on-chip reset predominant error latch driving a common external ERROR line, an ERROR-state on which also sets the latches and activates any inactive secondary controller to drive its chip to a first predetermined state and to reset its latch. When no ERROR signal remains, the secondary controllers cycle in synchronism through an ERROR routine, exiting to instruction control.