Patents by Inventor Mark A. Santaniello
Mark A. Santaniello has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10936038Abstract: A computing device may comprise a volatile memory and a non-volatile storage device. Upon system shutdown, contents of the volatile memory may be preserved by memory transfer operations from the volatile memory to the non-volatile storage device. During memory preservation, the computing device may enter a low-power state. The low-power state may comprise suspension of power to a core of a processor while maintaining power to the processor's uncore, and disablement of interrupt signals not related to memory transfer operations. Power delivery to the core of the processor may be periodically resumed to initiate additional memory transfer operations.Type: GrantFiled: June 28, 2019Date of Patent: March 2, 2021Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Bryan Kelly, Mark Santaniello, Sriram Govindan, Anirudh Badam
-
Publication number: 20190324516Abstract: A computing device may comprise a volatile memory and a non-volatile storage device. Upon system shutdown, contents of the volatile memory may be preserved by memory transfer operations from the volatile memory to the non-volatile storage device. During memory preservation, the computing device may enter a low-power state. The low-power state may comprise suspension of power to a core of a processor while maintaining power to the processor's uncore, and disablement of interrupt signals not related to memory transfer operations. Power delivery to the core of the processor may be periodically resumed to initiate additional memory transfer operations.Type: ApplicationFiled: June 28, 2019Publication date: October 24, 2019Inventors: Bryan Kelly, Mark Santaniello, Sriram Govindan, Anirudh Badam
-
Patent number: 10359826Abstract: A computing device may comprise a processor, a volatile memory and a non-volatile storage device. An operating system or firmware of the device may cause one or more pages of the volatile memory to be treated, by applications executing on the computing device, as non-volatile memory pages. A maximum number of pages that may be treated as non-volatile may be determined based on an amount of energy available in a battery and an amount of energy needed to transfer a page of memory to the non-volatile storage device.Type: GrantFiled: July 28, 2017Date of Patent: July 23, 2019Assignee: Microsoft Technology Licensing, LLCInventors: Bryan D. Kelly, Mark A. Santaniello, Sriram Govindan, Anirudh Badam
-
Patent number: 10338659Abstract: A computing device may comprise a volatile memory and a non-volatile storage device. Upon system shutdown, contents of the volatile memory may be preserved by memory transfer operations from the volatile memory to the non-volatile storage device. During memory preservation, the computing device may enter a low-power state. The low-power state may comprise suspension of power to a core of a processor while maintaining power to the processor's uncore, and disablement of interrupt signals not related to memory transfer operations. Power delivery to the core of the processor may be periodically resumed to initiate additional memory transfer operations.Type: GrantFiled: August 1, 2017Date of Patent: July 2, 2019Assignee: Microsoft Technology Licensing, LLCInventors: Bryan Kelly, Mark Santaniello, Sriram Govindan, Anirudh Badam
-
Patent number: 10168756Abstract: Various techniques for managing power backup for computing devices are disclosed herein. In one embodiment, a method includes receiving data representing a backup capacity of one or more backup power units and data representing a backup power profile of one or more processing units sharing the one or more backup power units. A portion of the backup capacity may then be assigned to each of the one or more processing units based at least in part on both the received data representing the backup capacity of the one or more backup power units and the received data representing the profile of the one or more processing units.Type: GrantFiled: September 23, 2016Date of Patent: January 1, 2019Assignee: Microsoft Technology Licensing, LLCInventors: Badriddine Khessib, Bryan Kelly, Mark Santaniello, Chris Ong, John Siegler, Sriram Govindan, Shaun Harris
-
Patent number: 10091091Abstract: A direct network is described in which each resource is connected to a switching fabric via a set of two or more routing nodes. The routing nodes are distributed so as to satisfy at least one inter-node separation criterion. In one case, the separation criterion specifies that, for each resource, a number of routing nodes that share a same coordinate value with another routing node in the set (in a same coordinate dimension) is to be minimized. In some network topologies, such as a torus network, this means a number of unique loops of the direct network to which each resource is connected is to be maximized. The routing provisions described herein offer various performance benefits, such as improved latency-related performance.Type: GrantFiled: December 21, 2015Date of Patent: October 2, 2018Assignee: Microsoft Technology Licensing, LLCInventors: David T. Harper, Eric C. Peterson, Mark A. Santaniello
-
Publication number: 20170364134Abstract: A computing device may comprise a volatile memory and a non-volatile storage device. Upon system shutdown, contents of the volatile memory may be preserved by memory transfer operations from the volatile memory to the non-volatile storage device. During memory preservation, the computing device may enter a low-power state. The low-power state may comprise suspension of power to a core of a processor while maintaining power to the processor's uncore, and disablement of interrupt signals not related to memory transfer operations. Power delivery to the core of the processor may be periodically resumed to initiate additional memory transfer operations.Type: ApplicationFiled: August 1, 2017Publication date: December 21, 2017Inventors: Bryan Kelly, Mark Santaniello, Sriram Govindan, Anirudh Badam
-
Publication number: 20170329379Abstract: A computing device may comprise a processor, a volatile memory and a non-volatile storage device. An operating system or firmware of the device may cause one or more pages of the volatile memory to be treated, by applications executing on the computing device, as non-volatile memory pages. A maximum number of pages that may be treated as non-volatile may be determined based on an amount of energy available in a battery and an amount of energy needed to transfer a page of memory to the non-volatile storage device.Type: ApplicationFiled: July 28, 2017Publication date: November 16, 2017Inventors: Bryan D. Kelly, Mark A. Santaniello, Sriram Govindan, Anirudh Badam
-
Patent number: 9785374Abstract: Various techniques of managing storage devices in a computing system are described in this application. In one embodiment, a method includes receiving an input containing consumption data representing consumption of a storage device in one of the processing units and determining if the storage device in one of the processing units is consumed excessively. In response to determining that the storage device is consumed excessively, an indicator may be generated to indicate a potential program migration from the one of the processing units to another one of the processing units in the computing system.Type: GrantFiled: September 25, 2014Date of Patent: October 10, 2017Assignee: Microsoft Technology Licensing, LLCInventors: Mark Santaniello, Badriddine Khessib, Laura Caulfield, Bikash Sharma
-
Patent number: 9760147Abstract: A computing device may comprise a volatile memory and a non-volatile storage device. Upon system shutdown, contents of the volatile memory may be preserved by memory transfer operations from the volatile memory to the non-volatile storage device. During memory preservation, the computing device may enter a low-power state. The low-power state may comprise suspension of power to a core of a processor while maintaining power to the processor's uncore, and disablement of interrupt signals not related to memory transfer operations. Power delivery to the core of the processor may be periodically resumed to initiate additional memory transfer operations.Type: GrantFiled: January 22, 2016Date of Patent: September 12, 2017Assignee: Microsoft Technology Licensing, LLCInventors: Bryan Kelly, Mark Santaniello, Sriram Govindan, Anirudh Badam
-
Publication number: 20170249996Abstract: Technology relating to tuning for operating memory devices is disclosed. The technology includes a computing device that selectively configures operating parameters for at least one operating memory device based at least in part of performance characteristics for an application or other workload that the computing device has been requested to execute. This technology may be implemented, at least in part, in the firmware via a Basic Input/Output System (BIOS) or Unified Extensible Firmware Interface (UEFI) of the computing device. Further, this technology may be employed by a computing device that is executing workloads on behalf of a distributed computing system, e.g., in a data center. Such data centers may include, for example, thousands of computing devices and even more operating memory devices.Type: ApplicationFiled: February 26, 2016Publication date: August 31, 2017Inventors: Mark W. Gottscho, Mohammed Shoaib, Sriram Govindan, Mark Santaniello, Bikash Sharma, J. Michael Andrewartha, Jie Liu, Badriddine Khessib
-
Patent number: 9746895Abstract: A computing device may comprise a processor, a volatile memory and a non-volatile storage device. An operating system or firmware of the device may cause one or more pages of the volatile memory to be treated, by applications executing on the computing device, as non-volatile memory pages. A maximum number of pages that may be treated as non-volatile may be determined based on an amount of energy available in a battery and an amount of energy needed to transfer a page of memory to the non-volatile storage device.Type: GrantFiled: January 22, 2016Date of Patent: August 29, 2017Assignee: Microsoft Technology Licensing, LLCInventors: Bryan Kelly, Mark Santaniello, Sriram Govindan, Anirudh Badam
-
Publication number: 20170212568Abstract: A computing device may comprise a volatile memory and a non-volatile storage device. Upon system shutdown, contents of the volatile memory may be preserved by memory transfer operations from the volatile memory to the non-volatile storage device. During memory preservation, the computing device may enter a low-power state. The low-power state may comprise suspension of power to a core of a processor while maintaining power to the processor's uncore, and disablement of interrupt signals not related to memory transfer operations. Power delivery to the core of the processor may be periodically resumed to initiate additional memory transfer operations.Type: ApplicationFiled: January 22, 2016Publication date: July 27, 2017Inventors: Bryan Kelly, Mark Santaniello, Sriram Govindan, Anirudh Badam
-
Publication number: 20170212573Abstract: A computing device may comprise a processor, a volatile memory and a non-volatile storage device. An operating system or firmware of the device may cause one or more pages of the volatile memory to be treated, by applications executing on the computing device, as non-volatile memory pages. A maximum number of pages that may be treated as non-volatile may be determined based on an amount of energy available in a battery and an amount of energy needed to transfer a page of memory to the non-volatile storage device.Type: ApplicationFiled: January 22, 2016Publication date: July 27, 2017Inventors: Bryan Kelly, Mark Santaniello, Sriram Govindan, Anirudh Badam
-
Publication number: 20170010644Abstract: Various techniques for managing power backup for computing devices are disclosed herein. In one embodiment, a method includes receiving data representing a backup capacity of one or more backup power units and data representing a backup power profile of one or more processing units sharing the one or more backup power units. A portion of the backup capacity may then be assigned to each of the one or more processing units based at least in part on both the received data representing the backup capacity of the one or more backup power units and the received data representing the profile of the one or more processing units.Type: ApplicationFiled: September 23, 2016Publication date: January 12, 2017Inventors: Badriddine Khessib, Bryan Kelly, Mark Santaniello, Chris Ong, John Siegler, Sriram Govindan, Shaun Harris
-
Patent number: 9483094Abstract: Various techniques for managing power backup for computing devices are disclosed herein. In one embodiment, a method includes receiving data representing a backup capacity of one or more backup power units and data representing a backup power profile of one or more processing units sharing the one or more backup power units. A portion of the backup capacity may then be assigned to each of the one or more processing units based at least in part on both the received data representing the backup capacity of the one or more backup power units and the received data representing the profile of the one or more processing units.Type: GrantFiled: February 11, 2014Date of Patent: November 1, 2016Assignee: Microsoft Technology Licensing, LLCInventors: Badriddine Khessib, Bryan Kelly, Mark Santaniello, Chris Ong, John Siegler, Sriram Govindan, Shaun Harris
-
Publication number: 20160112296Abstract: A direct network is described in which each resource is connected to a switching fabric via a set of two or more routing nodes. The routing nodes are distributed so as to satisfy at least one inter-node separation criterion. In one case, the separation criterion specifies that, for each resource, a number of routing nodes that share a same coordinate value with another routing node in the set (in a same coordinate dimension) is to be minimized. In some network topologies, such as a torus network, this means a number of unique loops of the direct network to which each resource is connected is to be maximized. The routing provisions described herein offer various performance benefits, such as improved latency-related performance.Type: ApplicationFiled: December 21, 2015Publication date: April 21, 2016Applicant: Microsoft Technology Licensing, LLCInventors: David T. HARPER, Eric C. PETERSON, Mark A. SANTANIELLO
-
Publication number: 20160092140Abstract: Various techniques of managing storage devices in a computing system are described in this application. In one embodiment, a method includes receiving an input containing consumption data representing consumption of a storage device in one of the processing units and determining if the storage device in one of the processing units is consumed excessively. In response to determining that the storage device is consumed excessively, an indicator may be generated to indicate a potential program migration from the one of the processing units to another one of the processing units in the computing system.Type: ApplicationFiled: September 25, 2014Publication date: March 31, 2016Inventors: Mark Santaniello, Badriddine Khessib, Laura Caulfield, Bikash Sharma
-
Patent number: 9258191Abstract: A direct network is described in which each resource is connected to a switching fabric via a set of two or more routing nodes. The routing nodes are distributed so as to satisfy at least one inter-node separation criterion. In one case, the separation criterion specifies that, for each resource, a number of routing nodes that share a same coordinate value with another routing node in the set (in a same coordinate dimension) is to be minimized. In some network topologies, such as a torus network, this means a number of unique loops of the direct network to which each resource is connected is to be maximized. The routing provisions described herein offer various performance benefits, such as improved latency-related performance.Type: GrantFiled: December 13, 2012Date of Patent: February 9, 2016Assignee: Microsoft Technology Licensing, LLCInventors: David T. Harper, Eric C. Peterson, Mark A. Santaniello
-
Publication number: 20150227181Abstract: Various techniques for managing power backup for computing devices are disclosed herein. In one embodiment, a method includes receiving data representing a backup capacity of one or more backup power units and data representing a backup power profile of one or more processing units sharing the one or more backup power units. A portion of the backup capacity may then be assigned to each of the one or more processing units based at least in part on both the received data representing the backup capacity of the one or more backup power units and the received data representing the profile of the one or more processing units.Type: ApplicationFiled: February 11, 2014Publication date: August 13, 2015Applicant: Microsoft CorporationInventors: Badriddine Khessib, Bryan Kelly, Mark Santaniello, Chris Ong, John Siegler, Sriram Govindan, Shaun Harris