Abstract: Methods, systems, and apparatuses for a foldable fabric-based semiconductor package (FFP) that can assist with charging a secondary cell are described. An FFP includes: a ground plane; a first component over the ground plane; a second component adjacent to the ground plane; a third component adjacent to the second component; a molding compound encapsulating the ground plane, the first component, the second component, and the third component; a first fabric layer on a top side of the molding compound; and a second fabric layer on a bottom side of the molding compound. Each of the first, second, and third components includes one or more semiconductor dies. The third component is electrically coupled to each of the first and second components. The first and second components can wireless charge the secondary cell. The third component can power the first and second components. The ground plane can protect against electromagnetic signals.

Abstract: Methods, systems, and apparatuses for a foldable fabric-based semiconductor package (FFP) that can assist with charging a secondary cell are described. An FFP includes: a ground plane; a first component over the ground plane; a second component adjacent to the ground plane; a third component adjacent to the second component; a molding compound encapsulating the ground plane, the first component, the second component, and the third component; a first fabric layer on a top side of the molding compound; and a second fabric layer on a bottom side of the molding compound. Each of the first, second, and third components includes one or more semiconductor dies. The third component is electrically coupled to each of the first and second components. The first and second components can wireless charge the secondary cell. The third component can power the first and second components. The ground plane can protect against electromagnetic signals.

Abstract: Embodiments of the invention are disclosed that include a low power memory and a low power data path.

Abstract: Embodiments of the invention are disclosed that include a low power memory and a low power data path.

Abstract: Embodiments are disclosed that include a low power memory and/or a low power data path. One particular embodiment, for example, includes a technique to reduce power consumption. In one particular embodiment, for example, a grouping of bits, such as a 32-bit word, for example, is stored in inverted form if more than half of the bits have a bit value of logic “1” rather than logic “0.” Likewise, in this embodiment, if more than half of the bits have a bit value of logic “0” rather than logic “1,” then the grouping of bits is not stored in inverted form.

Abstract: A method for conserving power during a cache memory operation is disclosed. The validity and the parity of the tag address are checked. If the tag is invalid or the parity bit does not check, the tag is not read and a tag comparison is not performed, such that the data is accessed from the main memory. Otherwise, the tag address bits are selected in a plurality of tag subsets. A first tag subset of the plurality of tag subsets is compared with a respective first subset of the tag field of the memory address bits. A first compare signal indicative of the result of the first comparison is outputted. The cache memory operation is interrupted if the first compare signal indicates the first tag subset does not match the respective first subset of the tag field of the memory address.

Abstract: A method and apparatus for improving the access time of a memory device is described. The location based timing scheme utilizes a subset of the address bits to adjust the timing of the sense amplifier enable in order to achieve a faster read of the information stored in the memory cell.

Abstract: A processor for executing a set of instructions, where each instruction in said set of instructions includes a set of operand references. The processor includes an instruction decoder for extracting the set of operand references from each instruction in the set of instructions; a register file decoder connected to the instruction decoder for receiving the set of operand references and generating a set of register data select signals; and, a register file connected to the register file decoder for receiving the set of register data select signals. Further, the register file includes: a set of registers; a first set of scoreboard bits; and, a second set of scoreboard bits; wherein for each signal in the set of register data select signals, the register file outputs: (1) a corresponding register from the set of registers; (2) a first corresponding scoreboard bit from the first set of scoreboard bits; and, (3) a second corresponding scoreboard bit from the second set of scoreboard bits.