Abstract: Aspects extend to methods, systems, and computer program products for remediating power loss at a server. Aspects of the invention increase the likelihood of gracefully shutting down a server and associated components in a data center when mains power is lost for a specified amount of time (e.g., an amount of time beyond transition to generator power). A server can include a management module (e.g., a BMC) and a watchdog module. When the management controller detects loss of power at a power supply unit, the management controller orchestrates a graceful shutdown of the server in response to power loss. When the management module is unresponsive, the watchdog module provides backup functionality for orchestrating a graceful shutdown in response to power loss. As such, data can be saved from RAM to more durable storage even when the management module is unresponsive.

Abstract: A data carrying cable to connect computing devices includes a first cable portion including a first conductor having a circular cross-section and a first gauge. A first port connector is connected to one end of the first cable portion. A second cable portion includes a second conductor having a circular cross-section and a second gauge that is different than the first gauge. The first conductor and the second conductor are arranged in series and are configured to carry a data signal between the computing devices.

Abstract: A data carrying cable to connect computing devices includes a first cable portion including a first conductor having a circular cross-section and a first gauge. A first port connector is connected to one end of the first cable portion. A second cable portion includes a second conductor having a circular cross-section and a second gauge that is different than the first gauge. The first conductor and the second conductor are arranged in series and are configured to carry a data signal between the computing devices.

Abstract: Embodiments of memory backup management in computing devices and associated methods of operations are disclosed therein. In one embodiment, a method of managing memory backup includes in response to a system error being detected, causing a memory controller to disengage from communicating with and controlling a hybrid memory device having a volatile memory module and a non-volatile memory module. The method can also include causing the hybrid memory device to copy data from the volatile memory module to the non-volatile memory module subsequent to disengaging the memory controller communicating with and controlling the storage device and without operating the main processor and the memory controller.

Abstract: Embodiments of memory backup management in computing devices and associated methods of operations are disclosed therein. In one embodiment, a method of managing memory backup includes in response to a system error being detected, causing a memory controller to disengage from communicating with and controlling a hybrid memory device having a volatile memory module and a non-volatile memory module. The method can also include causing the hybrid memory device to copy data from the volatile memory module to the non-volatile memory module subsequent to disengaging the memory controller communicating with and controlling the storage device and without operating the main processor and the memory controller.

Abstract: Certain computer systems having centralized power sources are described herein. In one embodiment, a computer system can include a processing unit and an enclosure containing the processing unit. The processing unit includes a motherboard having a processor and a clock circuitry operatively coupled to the processor. The processing unit can also include a power supply that includes a first rail configured to supply power at a first voltage to the processor on the motherboard and a second rail configured to supply power at a second voltage to the clock circuitry on the motherboard. The motherboard does not include a coin-type battery electrically coupled to the clock circuitry.

Abstract: Aspects extend to methods, systems, and computer program products for remediating power loss at a server. Aspects of the invention increase the likelihood of gracefully shutting down a server and associated components in a data center when mains power is lost for a specified amount of time (e.g., an amount of time beyond transition to generator power). A server can include a management module (e.g., a BMC) and a watchdog module. When the management controller detects loss of power at a power supply unit, the management controller orchestrates a graceful shutdown of the server in response to power loss. When the management module is unresponsive, the watchdog module provides backup functionality for orchestrating a graceful shutdown in response to power loss. As such, data can be saved from RAM to more durable storage even when the management module is unresponsive.

Abstract: A volatile memory data save subsystem may include a coupling to a shared power source such as a chassis or rack battery, or generator. A data save trigger controller sends a data save command toward coupled volatile memory device(s) such as NVDIMMs and PCIe devices under specified conditions: a programmable amount of time passes without AC power, a voltage level drops below normal but is still sufficient to power the volatile memory device during a data save operation, the trigger controller is notified of an operating system shutdown command, or the trigger controller is notified of an explicit data save command without a system shutdown command. NVDIMMs can avoid reliance on dedicated supercapacitors and dedicated batteries. An NVDIMM may perform an asynchronous DRAM reset in response to the data save command. Voltage step downs may be coordinated among power supplies. After data is saved, power cycles and the system reboots.

Abstract: A volatile memory data save subsystem may include a coupling to a shared power source such as a chassis or rack battery, or generator. A data save trigger controller sends a data save command toward coupled volatile memory device(s) such as NVDIMMs and PCIe devices under specified conditions: a programmable amount of time passes without AC power, a voltage level drops below normal but is still sufficient to power the volatile memory device during a data save operation, the trigger controller is notified of an operating system shutdown command, or the trigger controller is notified of an explicit data save command without a system shutdown command. NVDIMMs can avoid reliance on dedicated supercapacitors and dedicated batteries. An NVDIMM may perform an asynchronous DRAM reset in response to the data save command. Voltage step downs may be coordinated among power supplies. After data is saved, power cycles and the system reboots.

Abstract: To provide fault-tolerant, spread spectrum clock signals, a plurality of processing modules having respective spread spectrum control circuits are provided. Clock signals of redundant clock sources are provided to the plurality of processing modules. Failover control logic selects a corresponding one of the clock signals from the redundant clock sources for use in each of the processing modules. Frequency spreading is applied to the corresponding selected clock signal in each of at least some of the plurality of processing module.

Abstract: To provide fault-tolerant, spread spectrum clock signals, a plurality of processing modules having respective spread spectrum control circuits are provided. Clock signals of redundant clock sources are provided to the plurality of processing modules. Failover control logic selects a corresponding one of the clock signals from the redundant clock sources for use in each of the processing modules. Frequency spreading is applied to the corresponding selected clock signal in each of at least some of the plurality of processing module.

Abstract: Apparatus for configuring input/output signal levels of interfacing logic circuits operating at different voltage levels comprises: a logic circuit for operating at a first voltage level; a bank of input/output gates coupled to the logic circuit for interfacing input/output signals at a second voltage level, different from the first voltage level, to the logic circuit, the bank of gates including a port for setting the operational voltage level thereof; and a control circuit coupled to the port and governed by a control signal to configure the operational voltage level of the bank of gates to render the logic circuit and the interfacing input/output signals voltage level compatible.

Abstract: A system comprises plural electronic modules, at least one interconnect structure and plural power supplies. The electronic modules communicate over the interconnect structure. The system further comprises plural redundant manager modules to perform management tasks with respect to the at least one interconnect structure and the power supplies.

Abstract: Apparatus for configuring input/output signal levels of interfacing logic circuits operating at different voltage levels comprises: a logic circuit for operating at a first voltage level; a bank of input/output gates coupled to the logic circuit for interfacing input/output signals at a second voltage level, different from the first voltage level, to the logic circuit, the bank of gates including a port for setting the operational voltage level thereof; and a control circuit coupled to the port and governed by a control signal to configure the operational voltage level of the bank of gates to render the logic circuit and the interfacing input/output signals voltage level compatible.

Abstract: Apparatus for configuring input/output signal levels of interfacing logic circuits operating at different voltage levels comprises: a logic circuit for operating at a first voltage level; a bank of input/output gates coupled to the logic circuit for interfacing input/output signals at a second voltage level, different from the first voltage level, to the logic circuit, the bank of gates including a port for setting the operational voltage level thereof; and a control circuit coupled to the port and governed by a control signal to configure the operational voltage level of the bank of gates to render the logic circuit and the interfacing input/output signals voltage level compatible.

Abstract: Apparatus for configuring input/output signal levels of interfacing logic circuits operating at different voltage levels comprises: a logic circuit for operating at a first voltage level; a bank of input/output gates coupled to the logic circuit for interfacing input/output signals at a second voltage level, different from the first voltage level, to the logic circuit, the bank of gates including a port for setting the operational voltage level thereof; and a control circuit coupled to the port and governed by a control signal to configure the operational voltage level of the bank of gates to render the logic circuit and the interfacing input/output signals voltage level compatible.

Abstract: The invention relates with an optical bench for optoelectronic packages comprising a rigid insulating substrate, the substrate having a top surface along which it is defined an optical axis, the substrate comprising: a device region for mounting at least an optoelectronic device in alignment with the optical axis, and a fixing region adjacent to the device region for affixing at least an optical component in alignment with the optical axis. The substrate further comprises a third region provided with metallised tracks, the third region extending over the substrate top surface along at least part of one side of the fixing region in a direction substantially parallel to the optical axis. The invention also relates with an optical bench comprising: a single baseplate having a device region and a fixing region; a welding platform mounted directly on said fixing region; a heat sink mounted directly on said device region; and an optoelectronic device directly mounted on said heat sink.

Abstract: The invention relates with an optical bench for optoelectronic packages comprising a rigid insulating substrate, the substrate having a top surface along which it is defined an optical axis, the substrate comprising: a device region for mounting at least an optoelectronic device in alignment with the optical axis, and a fixing region adjacent to the device region for affixing at least an optical component in alignment with the optical axis. The substrate further comprises a third region provided with metallised tracks, the third region extending over the substrate top surface along at least part of one side of the fixing region in a direction substantially parallel to the optical axis. The invention also relates with an optical bench comprising: a single baseplate having a device region and a fixing region; a welding platform mounted directly on said fixing region; a heat sink mounted directly on said device region; and an optoelectronic device directly mounted on said heat sink.