Abstract: Systems and methods for verifying that light absorption is caused by a targeted gaseous chemical compound. A first transmittance of light, either generated at, or filtered to, a first wavelength range and a second transmittance of light, either generated at, or filtered to, a second wavelength range are measured by first and second photon detectors. A ratio of the first and second measured transmittance is determined and that ratio is compared to a transmittance ratio associated with a targeted gaseous chemical compound to verify that the light absorption is caused by the targeted gaseous chemical compound.

Abstract: Systems and methods for verifying that light absorption is caused by a targeted gaseous chemical compound. A first transmittance of light, either generated at, or filtered to, a first wavelength range and a second transmittance of light, either generated at, or filtered to, a second wavelength range are measured by first and second photon detectors. A ratio of the first and second measured transmittance is determined and that ratio is compared to a transmittance ratio associated with a targeted gaseous chemical compound to verify that the light absorption is caused by the targeted gaseous chemical compound.

Abstract: Systems and methods for verifying that light absorption is caused by a targeted gaseous chemical compound. A first transmittance of light, either generated at, or filtered to, a first wavelength range and a second transmittance of light, either generated at, or filtered to, a second wavelength range are measured by first and second photon detectors. A ratio of the first and second measured transmittance is determined and that ratio is compared to a transmittance ratio associated with a targeted gaseous chemical compound to verify that the light absorption is caused by the targeted gaseous chemical compound.

Abstract: Accelerated test of wireless devices. During normal device operation, protocol-specified delays in acknowledging received messages have the effect of reducing channel congestion, for example by piggybacking acknowledgements. When operating in a test environment, these protocol-specified delays are reduced or eliminated, thus reducing test time and increasing tester throughput. A first embodiment reduces or eliminates these protocol-specified delays in the tester. A second embodiment reduces or eliminates these protocol-specified delays in both the tester and the device under test.

Abstract: An apparatus for testing cellular base stations is provided. A base station tester is connected to a control link between the base station controller and the cellular base station to receive the fixed signal. The fixed link signal contains a voice channel and a control channel that may be selectively monitored by the base station tester. The base station tester is also connected to the radio frequency (RF) output of the cellular base station to receive the RF signal from the cellular base station. Both the RF signal and the fixed link signal are obtained in a non-invasive manner such that the cellular base station may remain in service during the testing process. By monitoring the fixed link directly, the base station tester may evaluate directly the reaction of the cellular base station with its RF signal to the commands received from the fixed link to perform parametric transmitter measurements.

Abstract: A test circuit (40) fabricated in an integrated circuit and connected to an I/O pin (36) of the packaged device (32) for providing information indicative of substrate process parameters. The test circuit (40) comprises a test transistor (24) connected to a pin (36) of the packaged device (32), and an isolation circuit (52) responsive to a signal on an input test terminal (48) for activating the test transistor (24). The isolation circuit (52) is responsive to the absence of the test signal for isolating the test transistor (24) from the pin (36), and thus isolating it from other functional circuitry (54) of the integrated circuit which is also connected to the pin (36).

Abstract: A microprocessor device used as an adapter for a communications loop of the closed-ring, token-passing, local area network type is disclosed. Each station on the ring has a host processor with a host CPU, a main memory, and a system bus. The microprocessor device therein which operates relatively independently from the host CPU, and which is coupled to the main memory by the system bus, includes a local CPU, a local read/write memory, an on-chip timer, a local bus and a bus arbiter. A transmit/receive controller is connected between the ring and the microprocessor device. This controller is coupled to the local bus to directly access the local read/write memory, also under control of the bus arbiter.

Abstract: A polyphase parity generator circuit for generating parity of multiple bit data values on a data bus during one or more phases of a bus cycle. The circuit includes a prestage circuit having a plurality of parallel decode circuits couplable to respective pairs of input data lines. Each decode circuit has an odd and even output line for providing output signals in response to odd or even number of 1's (or 0's) on an associated pair of row lines, respectively. The circuit includes a precharge discharge circuit coupled to the prestage circuit for generating a first parity signal in response to an odd number of 1's being on the input data lines and a second parity signal in response to an even number of 1's being on the input data lines.

Abstract: A frequency divide by n circuit, where n is an odd number, which includes means for splitting an incoming clock signal of frequency "f" into two non-overlapping complementary clock signals of frequency "f" and a shift register circuit. The shift register circuit is coupled to the signal splitting means and generates an output clock signal of frequency f/n in response to the two complementary clock signals. The output clock signal has a duty cycle equal to ((n-1)/2+D.sub.in)/n where D.sub.in is the duty cycle of the incoming clock signal. The output duty cycle is substantially independent of processing and operating conditions.

Abstract: A microprocessor device used as an adapter for a communications loop of the closed-ring, token-passing, local area network type. Each station on the ring has a host processor with a host CPU, a main memory, and a system bus. The microprocessor device, operating relatively independent of the host CPU, is coupled to the main memory by the system bus and includes a local CPU, a local read/write memory, an on-chip timer, a local bus and a bus arbiter. A transmit/receive controller is connected between the ring and the microprocessor device. This controller is coupled to the local bus to directly access the local read/write memory, also under control of the bus arbiter. The local CPU executes instructions fetched from a ROM accessed by the local bus, so the local CPU instruction fetch, the direct memory access from the transmit/receive controller for transmitting or receiving data frames, and the access from the host CPU for copying transmitted or received message frames, all contend for the local bus.

Abstract: A microprocessor device with an on-chip integrated auto-loaded timer is used in an adapter for a communications loop of the token-passing local area network type. The network has a number of stations coupled to a closed one-way signal path, and each station has a host processor with a host CPU and memory. The microprocessor device with integrated auto-loaded timer is part of an adapter coupled to the host processor. A message frame to be transmitted is copied into a local read/write memory in the adapter by way of the host system bus and a local bus, under initiation by the host CPU. A transmit-and-receive controller is coupled to the local bus to directly access the local read/write memory; when this station has access to the loop (i.e., receives a free token) the transmit-and-receive controller copies the message frame from the local read/write memory to the outgoing signal path, converting from parallel to serial.

Abstract: A read-only memory includes an array of rows and columns of memory cells with row lines and column lines associated with the array. The row lines are partitioned into groups that provide bits of a word on a number of output lines. Each group consists of an output line and a first voltage line with a plurality of row lines in between. A row selector is provided that receives an address signal for selecting a particular row in each group and connects a row line on one side of the selected row to the first voltage line and connects the row line on the other side of the row to the output line. A row precharge circuit is provided for precharging the row lines prior to the connection of a row line to an output line. Also provided is a column select circuit for receiving an address signal for connecting a particular column line to a second voltage line and for connecting one or more of the remaining column lines to one of the first voltage lines in order to reduce coupling.