Abstract: A unified blender/eye-surf circuit has a first signal path operable in a blender mode to blend phases of two phase-shifted clock signals of a first plurality of phase-shifted clock signals in a fixed ratio to generate a first blended clock signal, and operable in an eye-surf test mode to create variable phase offsets as weighted combinations of pairs phase-shifted clock signals of the first plurality of phase-shifted clock signals to generate the first blended clock signal. A second signal path is operable in the blender mode to blend phases of two phase-shifted clock signals of a second plurality of phase-shifted clock signals in a fixed ratio to generate a second blended clock signal, and operable in an eye-surf test mode to create variable phase offsets as weighted combinations of pairs phase-shifted clock signals of the second plurality of phase-shifted clock signals to generate the second blended clock signal.

Abstract: Loopback testing of a phase interpolator (PI) in a serial link system. A CDR loop operates in a loopback mode until a sampling clock signal locks to a first valid lock point in a first UI. The CDR loop includes the PI and a phase blender for blending weights of multiple clock signals, phase offset from each other, to apply a blender delay to the sampling clock signal. The PI phase code is stored, and the sampled loopback signal is checked for bit errors. The blender delay is repeatedly adjusted to phase shift the sampling clock signal, locking the sampling clock signal with the CDR loop, and checking for bit errors of the loopback signal, such that the blender delay sweeps across at least one UI. For each further UI, the PI phase code is adjusted to target a further valid lock point, and the blender delay is swept.

Abstract: Methods and systems are provided for operating an SAR ADC. The SAR ADC receives an analog signal and receives a first instance of conversion trigger signal. The SAR ADC, in response to receiving the first instance of the conversion trigger signal, generates a set of digital bit values corresponding to the analog signal. The SAR ADC, while one or more digital bit values corresponding to the analog signal are being generated, receives a second instance of the conversion trigger signal and temporarily stores the one or more digital bit values in response to receiving the second instance of the conversion trigger signal.

Abstract: Various example embodiments provide for handling phase interpolator (PI) integral non-linearity (INL) errors based on phase error measurements, which can be used in conjunction with clock data recovery (CDR) within a circuit, such as a data serializer/deserializer (SerDes) circuit. In particular, various example embodiments provide a PI system configured to measure and handle (e.g., reduce or correct) PI integral INL errors, where the PI system comprises a PI, a phase detector, a first-order path, a second-order loop, a phase integrator, a measurement component, and a look-up-table (LUT) component. For various example embodiments, the measurement component is configured to receive phase error information for an input data signal from the phase detector, receive frequency offset information from the second-order loop, receive phase position data for the input signal to the PI, and adjust mappings of one or more phase positions to the PI to reduce or correct non-linearity in the PI.

Abstract: Various embodiments provide for determining a capacitance (or capacitor value) of a circuit, determining a resistance-capacitance time constant (or RC time constant) of a circuit, or both. The circuit can comprise an integrated circuit (IC), such as a circuit implemented on die. An IC of some embodiments generates a frequency of a dock wave signal (e.g., an output signal) such that the clock wave signal encodes an effective capacitance of the IC, a RC time constant of the IC, or both. A component external to the IC, such as a controller, can receive the clock wave signal and determine the effective capacitance of the IC, the RC time constant of the IC, or both based on the received clock wave signal.

Abstract: Various embodiments provide for a circuit for measuring a frequency difference, a phase difference, or both of at least two clock signals (e.g., a reference clock signal and a feedback clock signal). In particular, various embodiments described herein may be used in a circuit design to convert an input phase of two clock signals to a frequency difference, which may be outputted in the form of a digital word. Additionally, various embodiments described herein may be used in a circuit design to convert an input phase of two clock signals as phase difference output, which may be outputted in the form of a digital word. Various embodiments can provide the frequency difference, the phase difference, or both in near real-time and with only a small amount of latency.

Abstract: A system for protecting walls/roofs from water uses a detachable flashing channel and a step flashing unit. The detachable flashing unit is a J shape structure which facilitates the protection of walls from rain water and the step flashing unit is a L shape structure also facilitating the protection of roofs from rain water.

Abstract: A laser pulse is injected into an unstable ring resonator-amplifier structure. Inside this resonator the laser pulse is amplified, spatially filtered and magnified. The laser pulse is recirculated in the resonator, being amplified, filtered and magnified on each pass. The magnification is chosen so that the beam passes through the amplifier in concentric non-overlapping regions similar to a single pass MOPA. After a number of passes around the ring resonator the laser pulse is spatially large enough to exit the ring resonator system by passing around an output mirror.

Abstract: A method is disclosed for apodizing a laser beam to smooth out the production of diffraction peaks due to optical discontinuities in the path of the laser beam, such method comprising introduction of a pattern of scattering elements for reducing the peak intensity in the region of such optical discontinuities, such pattern having smoothly tapering boundaries in which the distribution density of the scattering elements is tapered gradually to produce small gradients in the distribution density, such pattern of scattering elements being effective to reduce and smooth out the diffraction effects which would otherwise be produced. The apodizer pattern may be produced by selectively blasting a surface of a transparent member with fine abrasive particles to produce a multitude of minute pits. In one embodiment, a scattering apodizer pattern is employed to overcome diffraction patterns in a multiple element crystal array for harmonic conversion of a laser beam.

Abstract: A pair of uniaxial birefringent crystal elements are fixed together to form a serially arranged, integral assembly which, alternatively, provides either a linearly or elliptically polarized second-harmonic output wave or a linearly polarized third-harmonic output wave. The "extraordinary" or "e" directions of the crystal elements are oriented in the integral assembly to be in quadrature (90.degree.). For a second-harmonic generation in the Type-II-Type-II angle tuned case, the input fundamental wave has equal amplitude "o" and "e" components. For a third-harmonic generation, the input fundamental wave has "o" and "e" components whose amplitudes are in a ratio of 2:1 ("o":"e" reference first crystal). In the typical case of a linearly polarized input fundamental wave this can be accomplished by simply rotating the crystal assembly about the input beam direction by 10.degree..