Patents by Inventor Mark A. Tracy

Mark A. Tracy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11935972
    Abstract: Tri-layer semiconductor stacks for patterning features on solar cells, and the resulting solar cells, are described herein. In an example, a solar cell includes a substrate. A semiconductor structure is disposed above the substrate. The semiconductor structure includes a P-type semiconductor layer disposed directly on a first semiconductor layer. A third semiconductor layer is disposed directly on the P-type semiconductor layer. An outermost edge of the third semiconductor layer is laterally recessed from an outermost edge of the first semiconductor layer by a width. An outermost edge of the P-type semiconductor layer is sloped from the outermost edge of the third semiconductor layer to the outermost edge of the third semiconductor layer. A conductive contact structure is electrically connected to the semiconductor structure.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: March 19, 2024
    Assignee: Maxeon Solar Pte. Ltd.
    Inventors: Kieran Mark Tracy, David D. Smith, Venkatasubramani Balu, Asnat Masad, Ann Waldhauer
  • Patent number: 11502208
    Abstract: Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a back contact solar cell includes a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is disposed on a second thin dielectric layer disposed on the back surface of the substrate. A third thin dielectric layer is disposed laterally directly between the first and second polycrystalline silicon emitter regions. A first conductive contact structure is disposed on the first polycrystalline silicon emitter region. A second conductive contact structure is disposed on the second polycrystalline silicon emitter region.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: November 15, 2022
    Assignee: SunPower Corporation
    Inventors: Seung Bum Rim, David D. Smith, Taiqing Qiu, Staffan Westerberg, Kieran Mark Tracy, Venkatasubramani Balu
  • Publication number: 20220296612
    Abstract: The present invention provides improved pharmaceutical formulations for pulmonary delivery having improved chemical and physical stability of the therapeutic, prophylactic or diagnostic agent as compared to formulations known in the art. The improved pharmaceutical formulations of the invention for administration to the respiratory system of a patient for the treatment of a variety of disease conditions comprise a mass of biocompatible particles comprising an active agent, and a hydrogenated starch hydrosylate (HSH). The improvement over the prior art comprises the presence of HSH in the pharmaceutical formulation. The invention further relates to a method of treating diseases comprising administering the pharmaceutical formulations of the present invention to the respiratory system of a patient in need of treatment.
    Type: Application
    Filed: November 4, 2021
    Publication date: September 22, 2022
    Inventors: Charles D. Blizzard, Michael M. Lipp, Kevin L. Ward, Rachel Ryznal, Daniel LeBlanc, Mark A. Tracy, Rebecca Martin
  • Publication number: 20220262966
    Abstract: Tri-layer semiconductor stacks for patterning features on solar cells, and the resulting solar cells, are described herein. In an example, a solar cell includes a substrate. A semiconductor structure is disposed above the substrate. The semiconductor structure includes a P-type semiconductor layer disposed directly on a first semiconductor layer. A third semiconductor layer is disposed directly on the P-type semiconductor layer. An outermost edge of the third semiconductor layer is laterally recessed from an outermost edge of the first semiconductor layer by a width. An outermost edge of the P-type semiconductor layer is sloped from the outermost edge of the third semiconductor layer to the outermost edge of the third semiconductor layer. A conductive contact structure is electrically connected to the semiconductor structure.
    Type: Application
    Filed: May 6, 2022
    Publication date: August 18, 2022
    Inventors: Kieran Mark Tracy, David D. Smith, Venkatasubramani Balu, Asnat Masad, Ann Waldhauer
  • Patent number: 11355654
    Abstract: Tri-layer semiconductor stacks for patterning features on solar cells, and the resulting solar cells, are described herein. In an example, a solar cell includes a substrate. A semiconductor structure is disposed above the substrate. The semiconductor structure includes a P-type semiconductor layer disposed directly on a first semiconductor layer. A third semiconductor layer is disposed directly on the P-type semiconductor layer. An outermost edge of the third semiconductor layer is laterally recessed from an outermost edge of the first semiconductor layer by a width. An outermost edge of the P-type semiconductor layer is sloped from the outermost edge of the third semiconductor layer to the outermost edge of the third semiconductor layer. A conductive contact structure is electrically connected to the semiconductor structure.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: June 7, 2022
    Assignee: SunPower Corporation
    Inventors: Kieran Mark Tracy, David D. Smith, Venkatasubramani Balu, Asnat Masad, Ann Waldhauer
  • Publication number: 20220074925
    Abstract: The invention features a method of identifying therapeutically relevant compositions which include a therapeutic agent and 2,2-dimethylaminomethyl-[1-3]-dioxolane by screening for an effect of the agent on the liver of a model subject.
    Type: Application
    Filed: April 2, 2021
    Publication date: March 10, 2022
    Applicant: ARBUTUS BIOPHARMA CORPORATION
    Inventors: Marco A. Ciufolini, Thomas D. Madden, Michael J. Hope, Barbara Mui, Antonin de Fougerolles, Tatiana Novobrantseva, Anna Borodovsky, Akin Akinc, Mark Tracy, Pieter Rutter Cullis
  • Patent number: 10950740
    Abstract: Methods of fabricating solar cell emitter regions with differentiated P-type and N-type region architectures, and the resulting solar cells, are described herein. In an example, a solar cell includes an N-type semiconductor substrate having a light-receiving surface and a back surface. A plurality of N-type polycrystalline silicon regions is disposed on a first thin dielectric layer disposed on the back surface of the N-type semiconductor substrate. A plurality of P-type polycrystalline silicon regions is disposed on a second thin dielectric layer disposed in a corresponding one of a plurality of trenches interleaving the plurality of N-type polycrystalline silicon regions in the back surface of the N-type semiconductor substrate.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: March 16, 2021
    Assignee: SunPower Corporation
    Inventors: David D. Smith, Ann Waldhauer, Venkatasubramani Balu, Kieran Mark Tracy
  • Patent number: 10916280
    Abstract: Systems and methods for securely sharing a memory between an Embedded Controller (EC) and a Platform Controller Hub (PCH). In some embodiments, an IHS may include: a chipset; a flash device coupled to the chipset; and an EC coupled to the flash device via a first bus and to the chipset via a second bus, wherein the EC comprises a Read-Only Memory (ROM) portion and a Random Access Memory (RAM) portion, the EC configured to: retrieve EC firmware from the flash device via the first bus; store the retrieved EC firmware in the RAM portion; and prior to the execution of any instruction stored in the RAM portion, relinquish access to the flash device via the first bus.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: February 9, 2021
    Assignee: Dell Products, L.P.
    Inventors: Adolfo S. Montero, Mark Tracy Ellis
  • Patent number: 10804843
    Abstract: Methods of testing a semiconductor, and semiconductor testing apparatus, are described. In an example, a method for testing a semiconductor can include applying light on the semiconductor to induce photonic degradation. The method can also include receiving a photoluminescence measurement induced from the applied light from the semiconductor and monitoring the photonic degradation of the semiconductor from the photoluminescence measurement.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: October 13, 2020
    Assignee: SunPower Corporation
    Inventors: Xiuwen Tu, David Aitan Soltz, Michael C. Johnson, Seung Bum Rim, Taiqing Qiu, Yu-Chen Shen, Kieran Mark Tracy
  • Publication number: 20200225215
    Abstract: The invention features a method of identifying therapeutically relevant compositions which include a therapeutic agent and 2,2-dimethylaminomethyl-[1-3]-dioxolane by screening for an effect of the agent on the liver of a model subject.
    Type: Application
    Filed: June 14, 2019
    Publication date: July 16, 2020
    Inventors: Marco A. Ciufolini, Thomas D. Madden, Michael J. Hope, Barbara Mui, Antonin de Fougerolles, Tatiana Novobrantseva, Anna Borodovsky, Akin Akinc, Mark Tracy, Pieter Rutter Cullis
  • Publication number: 20200119220
    Abstract: Tri-layer semiconductor stacks for patterning features on solar cells, and the resulting solar cells, are described herein. In an example, a solar cell includes a substrate. A semiconductor structure is disposed above the substrate. The semiconductor structure includes a P-type semiconductor layer disposed directly on a first semiconductor layer. A third semiconductor layer is disposed directly on the P-type semiconductor layer. An outermost edge of the third semiconductor layer is laterally recessed from an outermost edge of the first semiconductor layer by a width. An outermost edge of the P-type semiconductor layer is sloped from the outermost edge of the third semiconductor layer to the outermost edge of the third semiconductor layer. A conductive contact structure is electrically connected to the semiconductor structure.
    Type: Application
    Filed: December 9, 2019
    Publication date: April 16, 2020
    Inventors: Kieran Mark Tracy, David D. Smith, Venkatasubramani Balu, Asnat Masad, Ann Waldhauer
  • Publication number: 20200075784
    Abstract: Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a back contact solar cell includes a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is disposed on a second thin dielectric layer disposed on the back surface of the substrate. A third thin dielectric layer is disposed laterally directly between the first and second polycrystalline silicon emitter regions. A first conductive contact structure is disposed on the first polycrystalline silicon emitter region. A second conductive contact structure is disposed on the second polycrystalline silicon emitter region.
    Type: Application
    Filed: November 8, 2019
    Publication date: March 5, 2020
    Inventors: Seung Bum Rim, David D. Smith, Taiqing Qiu, Staffan Westerberg, Kieran Mark Tracy, Venkatasubramani Balu
  • Patent number: 10505068
    Abstract: Tri-layer semiconductor stacks for patterning features on solar cells, and the resulting solar cells, are described herein. In an example, a solar cell includes a substrate. A semiconductor structure is disposed above the substrate. The semiconductor structure includes a P-type semiconductor layer disposed directly on a first semiconductor layer. A third semiconductor layer is disposed directly on the P-type semiconductor layer. An outermost edge of the third semiconductor layer is laterally recessed from an outermost edge of the first semiconductor layer by a width. An outermost edge of the P-type semiconductor layer is sloped from the outermost edge of the third semiconductor layer to the outermost edge of the third semiconductor layer. A conductive contact structure is electrically connected to the semiconductor structure.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: December 10, 2019
    Assignee: SunPower Corporation
    Inventors: Kieran Mark Tracy, David D. Smith, Venkatasubramani Balu, Asnat Masad, Ann Waldhauer
  • Publication number: 20190287588
    Abstract: Systems and methods for securely sharing a memory between an Embedded Controller (EC) and a Platform Controller Hub (PCH). In some embodiments, an IHS may include: a chipset; a flash device coupled to the chipset; and an EC coupled to the flash device via a first bus and to the chipset via a second bus, wherein the EC comprises a Read-Only Memory (ROM) portion and a Random Access Memory (RAM) portion, the EC configured to: retrieve EC firmware from the flash device via the first bus; store the retrieved EC firmware in the RAM portion; and prior to the execution of any instruction stored in the RAM portion, relinquish access to the flash device via the first bus.
    Type: Application
    Filed: March 15, 2018
    Publication date: September 19, 2019
    Applicant: Dell Products, L.P.
    Inventors: Adolfo S. Montero, Mark Tracy Ellis
  • Patent number: 10409019
    Abstract: An optical cable assembly is provided. The cable assembly includes a plurality of subunits surrounded by an outer cable jacket, a furcation unit and optical connectors coupled to the end of each of the subunits. Each of the subunits includes an inner jacket, a plurality of optical fibers; and a tensile strength element. The first tensile strength element and the inner jackets of each subunits are coupled to the furcation unit, and the optical fibers and tensile strength elements of each subunit extend through the furcation unit without being coupled to the furcation unit. The subunit tensile strength element and optical fibers of each subunit are balanced such that both experience axial loading applied to the assembly and, under various loading conditions, the compression of the subunits is controlled and/or the axial loading of the optical fibers is limited to allow proper function of the optical connector.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: September 10, 2019
    Assignee: Corning Optical Communications LLC
    Inventors: William Eric Caldwell, Terry Lee Ellis, William Carl Hurley, William Welch McCollough, Mark Tracy Paap
  • Publication number: 20190273467
    Abstract: Methods of testing a semiconductor, and semiconductor testing apparatus, are described. In an example, a method for testing a semiconductor can include applying light on the semiconductor to induce photonic degradation. The method can also include receiving a photoluminescence measurement induced from the applied light from the semiconductor and monitoring the photonic degradation of the semiconductor from the photoluminescence measurement.
    Type: Application
    Filed: March 11, 2019
    Publication date: September 5, 2019
    Inventors: Xiuwen Tu, David Aitan Soltz, Michael C. Johnson, Seung Bum Rim, Taiqing Qiu, Yu-Chen Shen, Kieran Mark Tracy
  • Publication number: 20190189813
    Abstract: Tri-layer semiconductor stacks for patterning features on solar cells, and the resulting solar cells, are described herein. In an example, a solar cell includes a substrate. A semiconductor structure is disposed above the substrate. The semiconductor structure includes a P-type semiconductor layer disposed directly on a first semiconductor layer. A third semiconductor layer is disposed directly on the P-type semiconductor layer. An outermost edge of the third semiconductor layer is laterally recessed from an outermost edge of the first semiconductor layer by a width. An outermost edge of the P-type semiconductor layer is sloped from the outermost edge of the third semiconductor layer to the outermost edge of the third semiconductor layer. A conductive contact structure is electrically connected to the semiconductor structure.
    Type: Application
    Filed: February 25, 2019
    Publication date: June 20, 2019
    Inventors: Kieran Mark Tracy, David D. Smith, Venkatasubramani Balu, Asnat Masad, Ann Waldhauer
  • Publication number: 20190097068
    Abstract: Methods of fabricating solar cell emitter regions with differentiated P-type and N-type region architectures, and the resulting solar cells, are described herein. In an example, a solar cell includes an N-type semiconductor substrate having a light-receiving surface and a back surface. A plurality of N-type polycrystalline silicon regions is disposed on a first thin dielectric layer disposed on the back surface of the N-type semiconductor substrate. A plurality of P-type polycrystalline silicon regions is disposed on a second thin dielectric layer disposed in a corresponding one of a plurality of trenches interleaving the plurality of N-type polycrystalline silicon regions in the back surface of the N-type semiconductor substrate.
    Type: Application
    Filed: November 26, 2018
    Publication date: March 28, 2019
    Inventors: David D. Smith, Ann Waldhauer, Venkatasubramani Balu, Kieran Mark Tracy
  • Patent number: 10230329
    Abstract: Methods of testing a semiconductor, and semiconductor testing apparatus, are described. In an example, a method for testing a semiconductor can include applying light on the semiconductor to induce photonic degradation. The method can also include receiving a photoluminescence measurement induced from the applied light from the semiconductor and monitoring the photonic degradation of the semiconductor from the photoluminescence measurement.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: March 12, 2019
    Assignee: SunPower Corporation
    Inventors: Xiuwen Tu, David Aitan Soltz, Michael C. Johnson, Seung Bum Rim, Taiqing Qiu, Yu-Chen Shen, Kieran Mark Tracy
  • Patent number: 10217878
    Abstract: Tri-layer semiconductor stacks for patterning features on solar cells, and the resulting solar cells, are described herein. In an example, a solar cell includes a substrate. A semiconductor structure is disposed above the substrate. The semiconductor structure includes a P-type semiconductor layer disposed directly on a first semiconductor layer. A third semiconductor layer is disposed directly on the P-type semiconductor layer. An outermost edge of the third semiconductor layer is laterally recessed from an outermost edge of the first semiconductor layer by a width. An outermost edge of the P-type semiconductor layer is sloped from the outermost edge of the third semiconductor layer to the outermost edge of the third semiconductor layer. A conductive contact structure is electrically connected to the semiconductor structure.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: February 26, 2019
    Assignee: SunPower Corporation
    Inventors: Kieran Mark Tracy, David D. Smith, Venkatasubramani Balu, Asnat Masad, Ann Waldhauer