Patents by Inventor Mark A. Valley

Mark A. Valley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Digital signal processor configured for multiprocessing
    Patent number: 5685005
    Abstract: A monolithic digital signal processor includes a core processor for performing digital signal computations, an I/O processor for controlling external access to and from the digital signal processor through an external port, first and second memory banks for storing instructions and data for the digital signal computations, and first and second buses interconnecting the core processor, the I/O processor and the memory banks. The core processor and the I/O processor access the memory banks on the first bus without interference on different clock phases of a clock cycle. The internal memory and the I/O processor of the digital signal processor are assigned to a region of a global memory space, which facilitates multiprocessing configurations. In a multiprocessor system, each digital signal processor is assigned a processor ID. The digital signal processor includes a bus arbitration circuit for controlling access to an external bus through the external port.
    Type: Grant
    Filed: October 4, 1994
    Date of Patent: November 4, 1997
    Assignee: Analog Devices, Inc.
    Inventors: Douglas Garde, Ronnin J. Yee, Mark A. Valley, Steven L. Cox
  • DMA controller responsive to transition of a request signal between first state and second state and maintaining of second state for controlling data transfer
    Patent number: 5634076
    Abstract: A monolithic digital signal processor includes a core processor for performing digital signal computations, an I/O processor for controlling external access to and from the digital signal processor through an external port, first and second memory banks for storing instructions and data for the digital signal computations, and first and second buses interconnecting the core processor, the I/O processor and the memory banks. The core processor and the I/O processor access the memory banks on the first bus without interference on different clock phases of a clock cycle. The internal memory and the I/O processor of the digital signal processor are assigned to a region of a global memory space, which facilitates multiprocessing configurations. In a multiprocessor system, each digital signal processor is assigned a processor ID. The digital signal processor includes a bus arbitration circuit for controlling access to an external bus through the external port.
    Type: Grant
    Filed: October 4, 1994
    Date of Patent: May 27, 1997
    Assignee: Analog Devices, Inc.
    Inventors: Douglas Garde, Mark A. Valley