Abstract: An integrated circuit die contains a total of at least 10,000 bipolar logica cells that dissipate at least 75 watts of power. To supply such a large amount of power to the logic cells, thin sputtered power busses of 3 .mu.m thickness overlie the logic cells; an insulating layer surrounds the power busses; openings in the insulating layer defined plating regions on the power busses; an electroplating base film lies throughout the plating regions; and, a thick plated conductor, of at least 16 .mu.m thickness, lies on the electroplating base film. By supplying power to the bipolar logic cells via the composite structure of the thin power busses and thick plated conductors, a noise margin problem in the logic cell output signals is avoided. With 16 .mu.m thick plated conductors, the total number of logic cells on the die can be increased until their total power dissipation reaches 75 watts. With 21 .mu.m thick plated conductors, total die power can be increased to 100 watts.

Abstract: In the disclosed method, dopant atoms of a first conductivity type are implanted into the surface of a semiconductor substrate to form a channel region of each transistor having a relatively high dopant density at a predetermined depth below the surface and a substantially lower dopant density at the surface. This eliminates reachthrough in the channel without adversely increasing the channels threshold voltage. Thereafter, dopant atoms of a second conductivity type are implanted into the substrate to form source and drain regions adjacent to the channels having a depth of less than 0.3 .mu.m below the surface. This minimizes the radius of curvature and corresponding depletion width at the respective junctions with the channel. Subsequently, a patterned insulating layer is formed on said surface at temperatures that are far below the insulating layer's flow point. This avoids diffusing the distribution of the implanted dopant atoms.

Abstract: This disclosure relates to a V-MOS field effect transistor which is provided with enhanced source capacitance to provide a single transistor dynamic memory cell. The formation of the source area is achieved by masking the silicon substrate, opening an aperture in the mask and then etching the silicon substrate in such a manner as to undercut the mask so that the mask provides a shield to subsequent ion implanting of the source area. Both P and N type dopants can be separately implanted with different energy levels so as to form an enhanced PN junction capacitance for the device. Such a field effect transistor can be achieved without the formation of a graded dopant concentration in the channel between the source and drain areas of the transistor.