Abstract: To speed up output clock alignment in a digital phase locked loop wherein a controlled oscillator generates synthesizer pulses that are divided to produce output pulses at a predetermined normal spacing and time location, and wherein during an alignment procedure the output pulses are moved in time in response to a delay value obtained by comparing a phase of the output pulses with a phase applied to the controlled oscillator averaged over a number of synthesizer pulses in a feedback circuit to align said output pulses with a reference clock taking into account hardware delay, a group of the output pulses is advanced during the alignment procedure to reduce the spacing between them. After determining the delay value averaged over the group of output pulses subsequent output pulses are restored to their normal spacing and time locations.

Abstract: A slave device for exchanging data with a master device over a serial interface sends data to the master device upon receipt of a command from the master device. A controller responsive to a command byte in a receive register commences transmission of data in the transmit register under the control of a clock signal prior to reception of a complete command.

Abstract: A low latency digital clock fault detector has an edge detector including a delay line generating pulses on edges o an incoming clock signal of a width determined by the length of said delay line. A watchdog timer with flip-flops in a pipeline configuration has a first input held at a static logic level, a second input receiving a reference clock, and a third reset input. The watchdog is being responsive to the pulses to maintain a stable output in the presence of said pulses and generate a fault indication in the absence of the pulses.

Abstract: To speed up output clock alignment in a digital phase locked loop wherein a controlled oscillator generates synthesizer pulses that are divided to produce output pulses at a predetermined normal spacing and time location, and wherein during an alignment procedure the output pulses are moved in time in response to a delay value obtained by comparing a phase of the output pulses with a phase applied to the controlled oscillator averaged over a number of synthesizer pulses in a feedback circuit to align said output pulses with a reference clock taking into account hardware delay, a group of the output pulses is advanced during the alignment procedure to reduce the spacing between them. After determining the delay value averaged over the group of output pulses subsequent output pulses are restored to their normal spacing and time locations.

Abstract: Master clock redundancy is provided for a digital phase locked loop having a digital controlled oscillator (DCO) driven by a master clock source, for example, a crystal oscillator. One of a plurality of a crystal oscillators generating clock signals is selected to drive the DCO. The performance of the crystal oscillators is monitored, and the DCO is switched from being driven by a previously selected crystal oscillator to a newly selected crystal oscillator upon loss of a clock signal from the previously selected crystal oscillator or when the performance of the previously selected crystal oscillator falls below a predetermined acceptable level.

Abstract: A slave device for exchanging data with a master device over a serial interface sends data to the master device upon receipt of a command from the master device. A controller responsive to a command byte in a receive register commences transmission of data in the transmit register under the control of a clock signal prior to reception of a complete command.

Abstract: A low latency digital clock fault detector has an edge detector including a delay line generating pulses on edges o an incoming clock signal of a width determined by the length of said delay line. A watchdog timer with flip-flops in a pipeline configuration has a first input held at a static logic level, a second input receiving a reference clock, and a third reset input. The watchdog is being responsive to the pulses to maintain a stable output in the presence of said pulses and generate a fault indication in the absence of the pulses.

Abstract: Master clock redundancy is provided for a digital phase locked loop having a digital controlled oscillator (DCO) driven by a master clock source, for example, a crystal oscillator. One of a plurality of a crystal oscillators generating clock signals is selected to drive the DCO. The performance of the crystal oscillators is monitored, and the DCO is switched from being driven by a previously selected crystal oscillator to a newly selected crystal oscillator upon loss of a clock signal from the previously selected crystal oscillator or when the performance of the previously selected crystal oscillator falls below a predetermined acceptable level.