Patents by Inventor Mark Adam Bachman

Mark Adam Bachman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100319967
    Abstract: A device fabrication method, according to which a tin-copper-alloy layer is formed adjacent to a copper-plated pad or pin that is used to electrically connect the device to external wiring. Advantageously, the tin-copper-alloy layer inhibits copper dissolution during a solder reflow process because that layer is substantially insoluble in liquid Sn—Ag—Cu (tin-silver-copper) solder alloys under typical solder reflow conditions and therefore shields the copper plating from direct physical contact with the liquefied solder.
    Type: Application
    Filed: June 28, 2007
    Publication date: December 23, 2010
    Applicant: AGERE SYSTEMS INC.
    Inventors: Ahmed Amin, Mark Adam Bachman, Frank A. Baiocchi, John A. Delucca, John W. Osenbach, Zhengpeng Xiong
  • Patent number: 7777333
    Abstract: A solder bump structure and an under bump metallurgical structure. An upper surface of a semiconductor substrate comprises a first conductive pad (200) disposed thereon. A passivation layer (202) overlies the upper surface. A second conductive pad (212) is disposed in an opening (204) in the passivation layer and in contact with the first conductive pad. The under bump metallurgical structure (300) encapsulates the second conductive pad, covering an upper surface and sidewalls surfaces of the second conductive pad, protecting both the first and the second conductive pads from environmental and processing effects. According to the present invention, the conventional second passivation layer is not required. Methods for forming the various structures are also presented.
    Type: Grant
    Filed: February 24, 2006
    Date of Patent: August 17, 2010
    Assignee: Agere Systems Inc.
    Inventors: Mark Adam Bachman, Donald Stephen Bitting, Daniel Patrick Chesire, Taeho Kook, Sailesh Mansinh Merchant
  • Patent number: 7724359
    Abstract: Many electronic entities such as integrated circuits and discrete power devices have contact pads formed from successively deposited layers of nickel and a second metal such as gold. The resulting pad structure is used to make external electrical connection such as solder connection. Problems associated with failure of such connections are avoidable by inspecting the surface of the nickel layer for excessive small particle formation.
    Type: Grant
    Filed: May 27, 2008
    Date of Patent: May 25, 2010
    Assignee: Agere Systems Inc.
    Inventors: Ahmed Nur Amin, Mark Adam Bachman, Frank A. Baiocchi, John Michael DeLucca, John William Osenbach
  • Patent number: 7671436
    Abstract: Assemblies involving integrated circuit dies (e.g. packaged integrated circuits) and packaged dies electrically connected to circuit boards at times mechanically fail at conducting pads used for electrical interconnection. Such failure is mitigated by underlying appropriate pads with a compliant region having specific characteristics.
    Type: Grant
    Filed: May 2, 2008
    Date of Patent: March 2, 2010
    Assignee: Agere Systems Inc.
    Inventors: Ahmed Nur Amin, Mark Adam Bachman, David Lee Crouthamel, John William Osenbach, Brian Thomas Vaccaro
  • Publication number: 20090298286
    Abstract: Many electronic entities such as integrated circuits and discrete power devices have contact pads formed from successively deposited layers of nickel and a second metal such as gold. The resulting pad structure is used to make external electrical connection such as solder connection. Problems associated with failure of such connections are avoidable by inspecting the surface of the nickel layer for excessive small particle formation.
    Type: Application
    Filed: May 27, 2008
    Publication date: December 3, 2009
    Inventors: Ahmed Nur Amin, Mark Adam Bachman, Frank A. Baiocchi, John Michael DeLucca, John William Osenbach
  • Publication number: 20090273078
    Abstract: Assemblies involving integrated circuit dies (e.g. packaged integrated circuits) and packaged dies electrically connected to circuit boards at times mechanically fail at conducting pads used for electrical interconnection. Such failure is mitigated by underlying appropriate pads with a compliant region having specific characteristics.
    Type: Application
    Filed: May 2, 2008
    Publication date: November 5, 2009
    Inventors: Ahmed Nur Amin, Mark Adam Bachman, David Lee Crouthamel, John William Osenbach, Brian Thomas Vaccaro
  • Publication number: 20090072393
    Abstract: A solder bump structure and an under bump metallurgical structure. An upper surface of a semiconductor substrate comprises a first conductive pad (200) disposed thereon. A passivation layer (202) overlies the upper surface. A second conductive pad (212) is disposed in an opening (204) in the passivation layer and in contact with the first conductive pad. The under bump metallurgical structure (300) encapsulates the second conductive pad, covering an upper surface and sidewalls surfaces of the second conductive pad, protecting both the first and the second conductive pads from environmental and processing effects. According to the present invention, the conventional second passivation layer is not required. Methods for forming the various structures are also presented.
    Type: Application
    Filed: February 24, 2006
    Publication date: March 19, 2009
    Applicant: Agere Systems Inc.
    Inventors: Mark Adam Bachman, Donald Stephen Bitting, Daniel Patrick Chesire, Taeho Kook, Sailesh Mansinh Merchant
  • Patent number: 7479695
    Abstract: An assembly comprises a stiffener, a circuit substrate and an integrated circuit (IC) chip. The stiffener has a surface with a first region and a second region. The circuit substrate covers the first region, while the IC chip overlies at least a portion of each of the first and second regions. Moreover, the assembly further comprises a plurality of first solder bumps and a plurality of second solder bumps. The first solder bumps contact both the IC chip and the circuit substrate. The second solder bumps are larger than the first solder bumps, contact the IC chip and are disposed above the second region of the stiffener.
    Type: Grant
    Filed: March 14, 2006
    Date of Patent: January 20, 2009
    Assignee: Agere Systems Inc.
    Inventors: Mark Adam Bachman, David L. Crouthamel
  • Patent number: 7328830
    Abstract: An integrated circuit structure and a method for fabricating the structure. The method comprises forming a copper bond pad for attaching the integrated circuit to a package. Copper oxide is removed from the pad by reduction in a hydrogen ion atmosphere. For attaching the integrated circuit to a bump-bonding package an under-bump metallization layer is formed over the reduced copper pad and a solder bump formed thereover. The process can also be employed in a wire bonding process by forming an aluminum layer overlying the cleaned copper pad. The structure of the present invention comprises a copper pad formed in a substrate. A passivation layer defining an opening therein overlies the copper pad. A under-bump metallization layer is disposed in the opening and a solder bump overlies the metallization layer. Alternatively, the structure further comprises an aluminum pad disposed overlying the reduced copper pad.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: February 12, 2008
    Assignee: Agere Systems Inc.
    Inventors: Mark Adam Bachman, Daniel Patrick Chesire, Sailesh Mansinh Merchant
  • Patent number: 7221173
    Abstract: An interface assembly (20) and method for testing a semiconductor wafer prior to performing a flip chip bumping process are provided. The interface assembly includes a flip chip bonding pad (24) having a region (28) for performing the bumping process. A test pad (22) is integrally constructed with the bonding pad and includes a probe region (26) for performing wafer-level testing prior to performing the bumping process. The integral construction of the bonding and testing pads avoids, for example, an introduction of propagation delays to test signals passing therethrough, thereby improving the accuracy and reliability of wafer test results.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: May 22, 2007
    Assignee: Agere Systems, Inc.
    Inventors: Mark Adam Bachman, Daniel Patrick Chesire, Taeho Kook, Sailesh M. Merchant
  • Patent number: 6960836
    Abstract: Disclosed herein is a reinforcing system and method for reinforcing a contact pad of an integrated circuit. Specifically exemplified is a system and method that comprises a reinforcing structure interposed between a top contact pad layer and an underlying metal layer.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: November 1, 2005
    Assignee: Agere Systems, Inc.
    Inventors: Mark Adam Bachman, Daniel Patrick Chesire, Sailesh Mansinh Merchant, John William Osenbach, Kurt George Steiner
  • Publication number: 20040182915
    Abstract: An integrated circuit structure and a method for fabricating the structure. The method comprises forming a copper bond pad for attaching the integrated circuit to a package. Copper oxide is removed from the pad by reduction in a hydrogen ion atmosphere. For attaching the integrated circuit to a bump-bonding package an under-bump metallization layer is formed over the reduced copper pad and a solder bump formed thereover. The process can also be employed in a wire bonding process by forming an aluminum layer overlying the cleaned copper pad. The structure of the present invention comprises a copper pad formed in a substrate. A passivation layer defining an opening therein overlies the copper pad. A under-bump metallization layer is disposed in the opening and a solder bump overlies the metallization layer. Alternatively, the structure further comprises an aluminum pad disposed overlying the reduced copper pad.
    Type: Application
    Filed: December 19, 2003
    Publication date: September 23, 2004
    Inventors: Mark Adam Bachman, Daniel Patrick Chesire, Sailesh Mansinh Merchant