Patents by Inventor Mark Alan Einkauf

Mark Alan Einkauf has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5977983
    Abstract: A method and apparatus that adjusts certain graphics processing procedures based on a selectable speed/quality (S/Q) adjustment gauge. The S/Q adjustment can be tuned within a predetermined range (e.g., 0 to 255) where on one side, speed is represented over image quality while on the other side, image quality is represented over speed. Settings between the ends give proportional representation for speed and quality. A first graphics process determines whether linear or perspective texture mapping processes are to be used on the selected polygon based on: 1) the size of the polygon measured against a predetermined size threshold; and 2) the relative perspective of the polygon measured against a perspective threshold. The S/Q setting alters these thresholds to alter the operation of the first graphics procedure. A second graphics process splits a selected polygon graphics primitive based on the relative perspective of the polygon compared to a predetermined perspective threshold.
    Type: Grant
    Filed: February 20, 1997
    Date of Patent: November 2, 1999
    Assignee: S3 Incorporated
    Inventors: Mark Alan Einkauf, Thomas A. Dye, Goran Devic
  • Patent number: 5949421
    Abstract: A polygon vertex sorting circuit for a three dimensional graphics computer system. The system of the present invention includes a swap configuration circuit coupled to receive a plurality of vertex address corresponding to a plurality of vertices of a polygon. The swap configuration circuit is coupled to an address input bus to receive the plurality of vertex addresses. An address output interface circuit is coupled to the swap configuration circuit. The address output interface circuit interfaces the output of the swap configuration circuit with an address output bus. A control circuit is coupled to the swap configuration circuit and the output interface circuit. The control circuit sorts the plurality of vertices by configuring the swap configuration circuit and the address output interface circuit to output a swapped vertex address via the address output bus in response to receiving one of the plurality of vertex addresses via the address input bus.
    Type: Grant
    Filed: March 31, 1997
    Date of Patent: September 7, 1999
    Assignee: Cirrus Logic, Inc.
    Inventors: Thomas M. Ogletree, Mark Alan Einkauf
  • Patent number: 5841443
    Abstract: The system and method of the present invention performs an iterative operation that subdivides selected polygons (e.g., triangles) having high perspective ratios into a plurality of smaller polygons to limit artifact creation during the rendering/texture map processes. The present invention is particularly well suited for interpolation driven rendering/texture map processes. Processing logic of the present invention analyzes each polygon stored in display list memory of a graphics accelerator or graphics subsystem and determines a perspective ratio between adjacent vertices of the polygon. If the perspective ratio is greater than a pre-selected limit, the edge bounded by the vertices is subdivided at the mid-point and new polygons are created. The process is iterative until all polygons have perspective ratios that are less than the pre-selected limit, at which time the object data can be displayed by the hardware.
    Type: Grant
    Filed: February 20, 1997
    Date of Patent: November 24, 1998
    Assignee: S3 Incorporated
    Inventor: Mark Alan Einkauf
  • Patent number: 5841442
    Abstract: A method for computing input parameters used in a non-homogeneous second order perspective texture mapping process using interpolation. The present invention receives a polygon primitive (e.g., triangle) including screen display coordinates and texture map coordinates for each vertex (vmin, vmid, and vmax). Based on vertex information including perspective weights, w, screen display coordinates and texture map coordinates are determined for midpoints (i and j) of the two triangle slopes opposite the triangle's major slope. Based on a determined quadratic equation of the triangle's major slope, screen coordinates and texture map coordinates are determined at several selected points (e.g., imain, jmain, and midmain) along the major slope that corresponds to the i, j, and vmid points. From these values, quadratic coefficients a1, a2, and du.sub.-- ortho.sub.-- add are computed and also quadratic coefficients b1, b2 and dv.sub.-- ortho.sub.-- add are computed. The above values, parameters u.sub.-- main, du.sub.
    Type: Grant
    Filed: December 30, 1996
    Date of Patent: November 24, 1998
    Assignee: Cirrus Logic, Inc.
    Inventors: Mark Alan Einkauf, Michael Kerry Larson