Abstract: A phase locked loop (PLL) circuit and a method for providing a transconductance in the PLL involve forming an input voltage to an operational amplifier by a loop filter. A voltage output of the operational amplifier controls a plurality of current mirrors. A current is formed through a first one of the current mirrors as a function of the input voltage, a resistance of a resistor, and a reference voltage. The reference voltage is directly provided by, or derived from, a reference signal. A second voltage formed in the first current mirror is fed back to the operational amplifier to maintain the current through the first current mirror, which current is then mirrored into at least a second one of the current mirrors to form an output current proportional to a difference between the input voltage and the reference voltage.

Abstract: Systems disclosed herein provide for a low-noise current mirror operable under low power supply requirements. Embodiments of the systems provide for a low input current path and a high input current path, wherein the current in the low current input path sees a higher voltage and the current in the high input current path sees a lower voltage. Embodiments of the system also provide for a cascode transistor in the high input current path.

Abstract: Systems and methods disclosed herein provide for a fractional feedback divider with reduced jitter at the output without increasing the input clock frequency and with minimal power increase. Embodiments of the system provide for interpolating, with a multiplexer, different output clock signals depending on whether an extra half period of resolution from the input clock is needed for a certain output clock cycle.

Abstract: A phase difference multiplier circuit is disclosed that includes first and second delay circuits to apply two different quantities of delay to first and second input signals. The first and second delay circuits may operate in a first mode where a first and smaller amount of delay is imparted to the respective input signals. The first and second input signals differ in phase, and a transition in the first signal will be followed by a similar transition in the second signal. Following the transition of the first signal reaching the input of the first delay circuit, the similar transition will reach the input of the second delay circuit. In response to the transition reaching the input of the second delay circuit, the first and second delay circuits are then operated to impart a second and larger amount of delay to the first and second signals.