Patents by Inventor Mark Alfred Hadley
Mark Alfred Hadley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9805227Abstract: Methods and apparatuses for selecting a subset of RFID tags are provided in some embodiments. These methods and apparatuses utilize the susceptibility to light by persistent nodes found in passive tags. Light can be used to intentionally reduce persistence times in a particular subset tags or even an individual tag. Then, persistent nodes can be used as a selection criterion to distinguish previously illuminated tags from non-illuminated tags. In other embodiments, a power circuit receives a RF input source and generates a direct current (DC) output voltage. The circuit includes a bias circuit to supply a gate to source bias, which is independent of the DC output voltage. The circuit further includes a voltage multiplier circuit that is coupled to the bias circuit. The voltage multiplier circuit has MOS transistors with one transistor to receive the gate to source bias.Type: GrantFiled: July 23, 2015Date of Patent: October 31, 2017Assignee: Ruizhang Technology Limited CompanyInventors: Mark Alfred Hadley, James Harold Atherton, Jay Tu, Edward John Boling, John Stephen Smith
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Patent number: 9218519Abstract: Methods and apparatuses for selecting a subset of RFID tags are provided in some embodiments. These methods and apparatuses utilize the susceptibility to light by persistent nodes found in passive tags. Light can be used to intentionally reduce persistence times in a particular subset tags or even an individual tag. Then, persistent nodes can be used as a selection criterion to distinguish previously illuminated tags from non-illuminated tags. In other embodiments, a power circuit receives a RF input source and generates a direct current (DC) output voltage. The circuit includes a bias circuit to supply a gate to source bias, which is independent of the DC output voltage. The circuit further includes a voltage multiplier circuit that is coupled to the bias circuit. The voltage multiplier circuit has MOS transistors with one transistor to receive the gate to source bias.Type: GrantFiled: March 8, 2013Date of Patent: December 22, 2015Assignee: Alien Technology CorporationInventors: Mark Alfred Hadley, James Harold Atherton, Jay Tu, Edward John Boling, John Stephen Smith
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Publication number: 20150332138Abstract: Methods and apparatuses for selecting a subset of RFID tags are provided in some embodiments. These methods and apparatuses utilize the susceptibility to light by persistent nodes found in passive tags. Light can be used to intentionally reduce persistence times in a particular subset tags or even an individual tag. Then, persistent nodes can be used as a selection criterion to distinguish previously illuminated tags from non-illuminated tags. In other embodiments, a power circuit receives a RF input source and generates a direct current (DC) output voltage. The circuit includes a bias circuit to supply a gate to source bias, which is independent of the DC output voltage. The circuit further includes a voltage multiplier circuit that is coupled to the bias circuit. The voltage multiplier circuit has MOS transistors with one transistor to receive the gate to source bias.Type: ApplicationFiled: July 23, 2015Publication date: November 19, 2015Inventors: Mark Alfred Hadley, James Harold Atherton, Jay Tu, Edward John Boling, John Stephen Smith
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Publication number: 20150169908Abstract: Methods and apparatuses for selecting a subset of RFID tags are provided in some embodiments. These methods and apparatuses utilize the susceptibility to light by persistent nodes found in passive tags. Light can be used to intentionally reduce persistence times in a particular subset tags or even an individual tag. Then, persistent nodes can be used as a selection criterion to distinguish previously illuminated tags from non-illuminated tags. In other embodiments, a power circuit receives a RF input source and generates a direct current (DC) output voltage. The circuit includes a bias circuit to supply a gate to source bias, which is independent of the DC output voltage. The circuit further includes a voltage multiplier circuit that is coupled to the bias circuit. The voltage multiplier circuit has MOS transistors with one transistor to receive the gate to source bias.Type: ApplicationFiled: September 12, 2014Publication date: June 18, 2015Inventors: Mark Alfred Hadley, James Harold Atherton, Jay Tu, Edward John Boling, John Stephen Smith
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Publication number: 20130300540Abstract: Methods and apparatuses for selecting a subset of RFID tags are provided in some embodiments. These methods and apparatuses utilize the susceptibility to light by persistent nodes found in passive tags. Light can be used to intentionally reduce persistence times in a particular subset tags or even an individual tag. Then, persistent nodes can be used as a selection criterion to distinguish previously illuminated tags from non-illuminated tags. In other embodiments, a power circuit receives a RF input source and generates a direct current (DC) output voltage. The circuit includes a bias circuit to supply a gate to source bias, which is independent of the DC output voltage. The circuit further includes a voltage multiplier circuit that is coupled to the bias circuit. The voltage multiplier circuit has MOS transistors with one transistor to receive the gate to source bias.Type: ApplicationFiled: March 8, 2013Publication date: November 14, 2013Inventors: Mark Alfred Hadley, James Harold Atherton, Jay Tu, Edward John Boling, John Stephen Smith
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Patent number: 8395505Abstract: Methods and apparatuses for selecting a subset of RFID tags are provided in some embodiments. These methods and apparatuses utilize the susceptibility to light by persistent nodes found in passive tags. Light can be used to intentionally reduce persistence times in a particular subset tags or even an individual tag. Then, persistent nodes can be used as a selection criterion to distinguish previously illuminated tags from non-illuminated tags. In other embodiments, a power circuit receives a RF input source and generates a direct current (DC) output voltage. The circuit includes a bias circuit to supply a gate to source bias, which is independent of the DC output voltage. The circuit further includes a voltage multiplier circuit that is coupled to the bias circuit. The voltage multiplier circuit has MOS transistors with one transistor to receive the gate to source bias.Type: GrantFiled: April 7, 2009Date of Patent: March 12, 2013Assignee: Alien Technology CorporationInventors: Mark Alfred Hadley, James Harold Atherton, Jay Tu, Edward John Boling, John Stephen Smith
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Publication number: 20120249303Abstract: Methods and apparatuses for selecting a subset of RFID tags are provided in some embodiments. These methods and apparatuses utilize the susceptibility to light by persistent nodes found in passive tags. Light can be used to intentionally reduce persistence times in a particular subset tags or even an individual tag. Then, persistent nodes can be used as a selection criterion to distinguish previously illuminated tags from non-illuminated tags. In other embodiments, a power circuit receives a RF input source and generates a direct current (DC) output voltage. The circuit includes a bias circuit to supply a gate to source bias, which is independent of the DC output voltage. The circuit further includes a voltage multiplier circuit that is coupled to the bias circuit. The voltage multiplier circuit has MOS transistors with one transistor to receive the gate to source bias.Type: ApplicationFiled: April 7, 2009Publication date: October 4, 2012Inventors: Mark Alfred Hadley, James Harold Atherton, Jay Tu, Edward John Boling, John Stephen Smith
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Publication number: 20080186185Abstract: Methods and apparatuses for the protection of radio frequency identification (RFID) devices are described. In one aspect, a static dissipative material is applied to a web of antenna structures. A coating of the static dissipative material is applied continuously across a plurality of antenna structures of a roll of the web material. An RFID integrated circuit (IC) is attached to the web of antenna structures with the dissipative coating, then subsequently tested on the roll. Additional processing is performed to the RFID tag to produce an RFID label.Type: ApplicationFiled: February 4, 2008Publication date: August 7, 2008Inventors: Scott John Herrmann, Mark Alfred Hadley, Gordon Samuel Wiggins Craig, John Berhard Hattick, Paul Stephen Drzaic, Eric Ryan Kanemoto
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Patent number: 7342490Abstract: Methods and apparatuses for the protection of radio frequency identification (RFID) devices are described. In one aspect, a static dissipative material is applied to a web of antenna structures. A coating of the static dissipative material is applied continuously across a plurality of antenna structures of a roll of the web material. An RFID integrated circuit (IC) is attached to the web of antenna structures with the dissipative coating, then subsequently tested on the roll. Additional processing is performed to the RFID tag to produce an RFID label.Type: GrantFiled: November 23, 2004Date of Patent: March 11, 2008Assignee: Alien Technology CorporationInventors: Scott John Herrmann, Mark Alfred Hadley, Gordon Samuel Wiggins Craig, John Berhard Hattick, Paul Stephen Drzaic, Eric Ryan Kanemoto
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Patent number: 7080444Abstract: An apparatus for dispensing blocks in a fluid over a substrate. The apparatus includes a first tube having a first end and a second end. A compression device is coupled to the first tube. A second tube is connected to the first tube to deliver a slurry having blocks to the first tube. The compression device pulsates at least one block in the slurry which is flowing through a portion of the first tube.Type: GrantFiled: February 28, 2002Date of Patent: July 25, 2006Assignee: Alien Technology CorporationInventors: Gordon S. W. Craig, Ming X. Chan, Cornelius V. Sutu, Omar R. Alvarado, Hoang Pham, Mark Alfred Hadley
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Patent number: 6590346Abstract: Method and apparatus for electrical devices. An electronic assembly comprises at least one object having a first electrical circuitry therein. The object is created and separated from a host substrate. The assembly further comprises a receiving substrate having at least one recess. A bottom conducting layer is deposited over the receiving substrate and the recess. The object is then coupled to the receiving substrate such that the object is deposited on the bottom conducting layer and recessed within the first recess and below a surface of the receiving substrate. An insulation layer having a plurality of vias is disposed over the receiving substrate to insulate the bottom conducting layer and the object. A top conducting is deposited over the insulation layer and is making electrical interconnections to the bottom conducting layer and the object through the vias.Type: GrantFiled: July 16, 2001Date of Patent: July 8, 2003Assignee: Alien Technology CorporationInventors: Mark Alfred Hadley, Randolph Wilfred Eisenhardt