Abstract: A system is disclosed that comprises a field programmable gate array (FPGA), a network interface, and hardware description code, wherein the hardware description code is compilable into a plurality of bit configuration files for loading onto the FPGA, wherein each bit configuration file defines a pipelined processing operation for a hardware template. The FPGA comprises configurable hardware logic, and the FPGA can be accessible over a network via the network interface for commanding the FPGA to load a bit configuration file from among the bit configuration files onto the FPGA to thereby configure hardware logic on the FPGA to perform the pipelined processing operation defined by the loaded bit configuration file, and wherein the FPGA is configured to (1) receive streaming data and (2) process the streaming data through the configured hardware logic to perform the pipelined processing operation defined by the loaded bit configuration file on the streaming data.

Abstract: Apparatuses and methods are disclosed for comparing a first biosequence string with a second biosequence string to assess similarity between those biosequence strings. For example, a field programmable gate array (FPGA) can be used to (1) detect substrings of the second biosequence string that are matches to substrings of the first biosequence string, and (2) map the detected substrings of the second biosequence string to corresponding positions in the first biosequence string where the detected substrings are located based on a data structure that links substrings of the first biosequence string to positions in the first biosequence string where the substrings of the first biosequence string are located. These operations can be used to seed an alignment between the first and second biosequence strings that permits comparisons to be performed over longer substrings of the first and second biosequence strings so that similarities between those longer substrings can be quantified.

Abstract: A system is disclosed that comprises a field programmable gate array (FPGA), a network interface, and hardware description code, wherein the hardware description code is compilable into a plurality of bit configuration files for loading onto the FPGA, wherein each bit configuration file defines a pipelined processing operation for a hardware template. The FPGA comprises configurable hardware logic, and the FPGA can be accessible over a network via the network interface for commanding the FPGA to load a bit configuration file from among the bit configuration files onto the FPGA to thereby configure hardware logic on the FPGA to perform the pipelined processing operation defined by the loaded bit configuration file, and wherein the FPGA is configured to (1) receive streaming data and (2) process the streaming data through the configured hardware logic to perform the pipelined processing operation defined by the loaded bit configuration file on the streaming data.

Abstract: Apparatuses and methods are disclosed for comparing a first biosequence string with a second biosequence string to assess similarity between those biosequence strings. For example, a field programmable gate array (FPGA) can be used to (1) detect substrings of the second biosequence string that are matches to substrings of the first biosequence string, and (2) map the detected substrings of the second biosequence string to corresponding positions in the first biosequence string where the detected substrings are located based on a data structure that links substrings of the first biosequence string to positions in the first biosequence string where the substrings of the first biosequence string are located. These operations can be used to seed an alignment between the first and second biosequence strings that permits comparisons to be performed over longer substrings of the first and second biosequence strings so that similarities between those longer substrings can be quantified.

Abstract: A system is disclosed that comprises a field programmable gate array (FPGA), a network interface, and a plurality of hardware templates. The FPGA comprises configurable hardware logic, and the hardware templates define a plurality of different pipelined processing operations. The FPGA can be accessible over a network via the network interface for commanding the FPGA to load a hardware template from among the hardware templates onto the FPGA to thereby configure hardware logic on the FPGA to perform the pipelined processing operation defined by the loaded hardware template, and wherein the FPGA is configured to (1) receive streaming data and (2) process the streaming data through the configured hardware logic to perform the pipelined processing operation defined by the loaded hardware template on the streaming data.

Abstract: A method and apparatus use hardware logic deployed on a reconfigurable logic device to process a stream of financial information at hardware speeds. The hardware logic can be configured to perform data reduction operations on the financial information stream. Examples of such data reductions operations include data processing operations to compute a latest stock price, a minimum stock price, and a maximum stock price.

Abstract: A system is disclosed that comprises a field programmable gate array (FPGA), a network interface, and a plurality of hardware templates. The FPGA comprises configurable hardware logic, and the hardware templates define a plurality of different pipelined processing operations. The FPGA can be accessible over a network via the network interface for commanding the FPGA to load a hardware template from among the hardware templates onto the FPGA to thereby configure hardware logic on the FPGA to perform the pipelined processing operation defined by the loaded hardware template, and wherein the FPGA is configured to (1) receive streaming data and (2) process the streaming data through the configured hardware logic to perform the pipelined processing operation defined by the loaded hardware template on the streaming data.

Abstract: Apparatuses and methods are disclosed for comparing a first biosequence string with a second biosequence string to assess similarity between those biosequence strings. For example, a field programmable gate array (FPGA) can be used to (1) detect substrings of the second biosequence string that are matches to substrings of the first biosequence string, and (2) map the detected substrings of the second biosequence string to corresponding positions in the first biosequence string where the detected substrings are located based on a data structure that links substrings of the first biosequence string to positions in the first biosequence string where the substrings of the first biosequence string are located. These operations can be used to seed an alignment between the first and second biosequence strings that permits comparisons to be performed over longer substrings of the first and second biosequence strings so that similarities between those longer substrings can be quantified.

Abstract: Methods and systems are disclosed where an FPGA offloads a plurality of processing tasks from a processor. The FPGA can process streaming data received via a network interface, and the FPGA can be controllable in response to control instructions received from the processor. The FPGA comprises resident hardware logic for a plurality of data processing engines that are combinable as a processing pipeline within the FPGA. In response to the control instructions, the FPGA can control which of the data processing engines are activated and which of the data processing engines are deactivated to selectively tap into the streaming data to perform pipelined processing operations on the streaming data via the activated data processing engines. The deactivated data processing engines remain on the FPGA and provide a pass through path for the streaming data whereby the deactivated data processing engines do not perform processing operations on streaming data received thereby.

Abstract: A system and method for performing similarity searching is disclosed wherein programmable logic devices such as field programmable gate arrays (FPGAs) can be used to implement Bloom filters for identifying possible matches between a query and data. The Bloom filters can be implemented in a parallel architecture where the different parallel Bloom filters share access to the same memory units. Further, a hash table may be generated to map a set of strings to keys. In other examples, the hash table may be used to map a set of substrings to a position in a larger string.

Abstract: A multi-functional data processing pipeline is disclosed where the multi-functional pipeline comprises a plurality of pipelined data processing engines, the plurality of pipelined data processing engines being configured to perform processing operations. The multi-functional pipeline can be configured to controllably activate or deactivate each of the pipelined data processing engines in the pipeline in response to control instructions and thereby define a function for the pipeline, each pipeline function being the combined functionality of each activated pipelined data processing engine in the pipeline. In example embodiments, the pipelined data processing engines can include correlation logic, and such pipelines can be used to accelerate convolutional layers in machine-learning technology such as convolutional neural networks.

Abstract: Methods and systems are disclosed where an FPGA offloads a plurality of processing tasks from a processor. The FPGA can process streaming data received via a network interface, and the FPGA can be controllable in response to control instructions received from the processor. The FPGA comprises resident hardware logic for a plurality of data processing engines that are combinable as a processing pipeline within the FPGA. In response to the control instructions, the FPGA can control which of the data processing engines are activated and which of the data processing engines are deactivated to selectively tap into the streaming data to perform pipelined processing operations on the streaming data via the activated data processing engines. The deactivated data processing engines remain on the FPGA and provide a pass through path for the streaming data whereby the deactivated data processing engines do not perform processing operations on streaming data received thereby.

Abstract: Methods and systems are disclosed where a plurality of precompiled hardware templates are stored in memory, each of the hardware templates being configured for loading onto a re-configurable logic device such as a FPGA to define a data processing operation to be performed by the re-configurable logic device, each of the data processing operations defined by the precompiled hardware templates having an associated performance characteristic. A processor selects a precompiled hardware template from a plurality of the precompiled hardware templates in the memory for loading onto the re-configurable logic device based at least in part on the associated performance characteristics of the data processing operations defined by the precompiled hardware templates.

Abstract: Methods and systems are disclosed where a plurality of precompiled hardware templates are stored in memory, each of the hardware templates being configured for loading onto a re-configurable logic device such as a FPGA to define a data processing operation to be performed by the re-configurable logic device, each of the data processing operations defined by the precompiled hardware templates having an associated performance characteristic. A processor selects a precompiled hardware template from a plurality of the precompiled hardware templates in the memory for loading onto the re-configurable logic device based at least in part on the associated performance characteristics of the data processing operations defined by the precompiled hardware templates.

Abstract: Methods and systems are disclosed where a plurality of precompiled hardware templates are stored in memory, each of the hardware templates being configured for loading onto a re-configurable logic device such as a FPGA to define a data processing operation to be performed by the re-configurable logic device, each of the data processing operations defined by the precompiled hardware templates having an associated performance characteristic. A processor selects a precompiled hardware template from a plurality of the precompiled hardware templates in the memory for loading onto the re-configurable logic device based at least in part on the associated performance characteristics of the data processing operations defined by the precompiled hardware templates.

Abstract: A system and method for performing similarity searching is disclosed wherein programmable logic devices such as field programmable gate arrays (FPGAs) can be used to implement Bloom filters for identifying possible matches between a query and data. The Bloom filters can be implemented in a parallel architecture where the different parallel Bloom filters share access to the same memory units. Further, a hash table may be generated to map a set of strings to keys. In other examples, the hash table may be used to map a set of substrings to a position in a larger string.

Abstract: A multi-functional data processing pipeline is disclosed where the multi-functional pipeline comprises a plurality of pipelined data processing engines, the plurality of pipelined data processing engines being configured to perform processing operations. The multi-functional pipeline can be configured to controllably activate or deactivate each of the pipelined data processing engines in the pipeline in response to control instructions and thereby define a function for the pipeline, each pipeline function being the combined functionality of each activated pipelined data processing engine in the pipeline. In example embodiments, the pipelined data processing engines can include correlation logic, and such pipelines can be used to accelerate convolutional layers in machine-learning technology such as convolutional neural networks.

Abstract: A system and method for performing similarity searching is disclosed wherein programmable logic devices such as field programmable gate arrays (FPGAs) can be used to implement Bloom filters for identifying possible matches between a query and data. The Bloom filters can be implemented in a parallel architecture where the different parallel Bloom filters share access to the same memory units.

Abstract: Methods and systems are disclosed where a plurality of precompiled hardware templates are stored in memory, each of the hardware templates being configured for loading onto a re-configurable logic device such as a FPGA to define a data processing operation to be performed by the re-configurable logic device, each of the data processing operations defined by the precompiled hardware templates having an associated performance characteristic. A processor selects a precompiled hardware template from a plurality of the precompiled hardware templates in the memory for loading onto the re-configurable logic device based at least in part on the associated performance characteristics of the data processing operations defined by the precompiled hardware templates.

Abstract: A re-configurable logic device such as a field programmable gate array (FPGA) can be used to deploy a data processing pipeline, the pipeline comprising a plurality of pipelined data processing engines, the plurality of pipelined data processing engines being configured to perform processing operations, wherein the pipeline comprises a multi-functional pipeline, and wherein the re-configurable logic device is further configured to controllably activate or deactivate each of the pipelined data processing engines in the pipeline in response to control instructions and thereby define a function for the pipeline, each pipeline function being the combined functionality of each activated pipelined data processing engine in the pipeline.