Abstract: A semiconductor device (100) comprising a leadframe (120) having an assembly pad (121) in a first horizontal plane (180), the pad's first surface (121a) with a semiconductor chip (110) attached; further a plurality of leads (122) in a parallel second horizontal plane (190) offset from the first plane in the direction of the attached chip, the leads having a third surface (122a) with bonding wires, and an opposite fourth surface (122b); a package (140) encapsulating leadframe, chip, and wires, the package having a fifth surface (140a) parallel to the first and second planes; a plurality of recess holes (150) in the package, each hole stretching from the fifth surface to the fourth surface of respective leads; and solder (160) filling the recess holes, the solder attached to the fourth lead surface and extending to the fifth package surface.

Abstract: A semiconductor device (100) comprising a leadframe (120) having an assembly pad (121) in a first horizontal plane (180), the pad's first surface (121a) with a semiconductor chip (110) attached; further a plurality of leads (122) in a parallel second horizontal plane (190) offset from the first plane in the direction of the attached chip, the leads having a third surface (122a) with bonding wires, and an opposite fourth surface (122b); a package (140) encapsulating leadframe, chip, and wires, the package having a fifth surface (140a) parallel to the first and second planes; a plurality of recess holes (150) in the package, each hole stretching from the fifth surface to the fourth surface of respective leads; and solder (160) filling the recess holes, the solder attached to the fourth lead surface and extending to the fifth package surface.

Abstract: A semiconductor device (100) comprising a leadframe (120) having an assembly pad (121) in a first horizontal plane (180), the pad's first surface (121a) with a semiconductor chip (110) attached; further a plurality of leads (122) in a parallel second horizontal plane (190) offset from the first plane in the direction of the attached chip, the leads having a third surface (122a) with bonding wires, and an opposite fourth surface (122b); a package (140) encapsulating leadframe, chip, and wires, the package having a fifth surface (140a) parallel to the first and second planes; a plurality of recess holes (150) in the package, each hole stretching from the fifth surface to the fourth surface of respective leads; and solder (160) filling the recess holes, the solder attached to the fourth lead surface and extending to the fifth package surface.

Abstract: Embodiments of the invention provide a method for forming a dual sided embedded die system. The method begins with starting material including a top surface and a bottom surface, a plurality of vias, a plurality of plated metal posts, die pads, and stiffeners. The surface are planarized to expose the included metal which is than selectively etching from die attach pad DAP areas to form cavities. Create a stiffener by using photo resist patterning and plating. Apply tacky tape. Attach a die. Laminate and grind. Remove tacky tape. Form redistribution layers RDLs and a solder mask. Mounting Surface Mount Devices.

Abstract: A circuit assembly includes a substrate having a substrate electrical circuit, opposite top and bottom substrate surfaces, and a substrate hole extending through the substrate. The circuit assembly also includes a discrete component assembly electrically connected to the substrate electrical circuit and a support member attached to the discrete component. At least a portion of the discrete component is physically mounted in the substrate hole.

Abstract: Embodiments of the invention provide a method for forming a dual sided embedded die system. The method begins with starting material including a top surface and a bottom surface, a plurality of vias, a plurality of plated metal posts, die pads, and stiffeners. The surface are planarized to expose the included metal which is than selectively etching from die attach pad DAP areas to form cavities. Create a stiffener by using photo resist patterning and plating. Apply tacky tape. Attach a die. Laminate and grind. Remove tacky tape. Form redistribution layers RDLs and a solder mask. Mounting Surface Mount Devices.

Abstract: A semiconductor device (100) comprising a leadframe (120) having an assembly pad (121) in a first horizontal plane (180), the pad's first surface (121a) with a semiconductor chip (110) attached; further a plurality of leads (122) in a parallel second horizontal plane (190) offset from the first plane in the direction of the attached chip, the leads having a third surface (122a) with bonding wires, and an opposite fourth surface (122b); a package (140) encapsulating leadframe, chip, and wires, the package having a fifth surface (140a) parallel to the first and second planes; a plurality of recess holes (150) in the package, each hole stretching from the fifth surface to the fourth surface of respective leads; and solder (160) filling the recess holes, the solder attached to the fourth lead surface and extending to the fifth package surface.

Abstract: A circuit assembly includes a substrate having a substrate electrical circuit, opposite top and bottom substrate surfaces, and a substrate hole extending through the substrate. The circuit assembly also includes a discrete component assembly electrically connected to the substrate electrical circuit and a support member attached to the discrete component. At least a portion of the discrete component is physically mounted in the substrate hole.

Abstract: A discrete component assembly includes a discrete component having a central longitudinal axis and having an outer surface with a laterally outermost point positioned at a first radial distance from the central longitudinal axis. The assembly includes a support structure mounted on the discrete component. The assembly also includes a plurality of contact pads electrically connected to the discrete component and mounted on the support structure at radial distances from the central longitudinal axis greater than the first radial distance.

Abstract: A process flow employing a liquid cleaning agent (510) such as flux to penetrate the interface between the glassy coats (402) and the surface of metal (120) and to delaminate the coats from the metal, and then, at elevated temperatures, to use the agent's vapor pressure to break up the glassy coats into smaller pieces (403). The glassy coats are prevented by their low density to penetrate into the molten solder. Finally, at ambient temperature, the floating filler debris is water-washed and rinsed away. Cleaning agents include low-viscosity liquids (oils) and flux, which do not decompose at elevated temperatures and are mixed with components operable to provide, at the elevated temperatures, the fumes for sufficient vapor pressure to break up and dislodge the coats from the metal contacts.

Abstract: Stacked semiconductor chip package system vertical interconnects and related methods are disclosed. A preferred embodiment of the invention includes a first semiconductor chip with a surface bearing a plurality of first fusible metallic coupling elements. A second semiconductor chip has a plurality of second fusible metallic coupling elements. The first and second fusible metallic coupling elements correspond at the adjoining surfaces of the first and second semiconductor chips when stacked, and are fused to form a gold-tin eutectic alloy fused metallic coupling vertically interconnecting the stacked chips.

Abstract: Disclosed are methods and devices for providing improved semiconductor packages and POP IC assemblies using the improved packages with reduced warping. According to disclosed embodiments of the inventions, a packaged semiconductor device for use in a POP assembly includes an encapsulated region generally defined by the substrate surface. The encapsulant is provided with contact apertures permitting external communication with contacts on the substrate and coupled to an encapsulated chip. Preferred embodiments of the invention are described in which the contact aperture sidewalls are angled within the range of approximately 10-30 degrees or more from vertical and in which the contact aperture is provided a gas release channel to permit gas to escape during reflow.

Abstract: A method, comprising bonding a first wire to a single die bond pad to form a first bond, bonding the first wire to a bond post to form a second bond, bonding a second wire to the first bond, and coupling the second wire to the bond post.

Abstract: The invention relates to microelectronic semiconductor device assemblies having vertically stacked semiconductor device layers. In a disclosed example of a preferred embodiment, a semiconductor device includes a base substrate, an interposing layer, and a second semiconductor device. The interposing layer features a thin insulating film with numerous electrical contacts on its surfaces for electrically coupling with electrical contacts on the adjacent layers. The interposing layer further includes electrical contacts for coupling with one or more non-adjacent layers. Particular examples of preferred embodiments of the invention disclose the use of polyimide film for the interposing layer material and metal studs for non-adjacent layer contacts.

Abstract: A solder ball pad that includes a substrate and a bonding pad attached to the substrate. The bonding pad has a bonding pad surface and a bonding pad edge. The solder ball pad also includes a solder mask attached to the substrate in which the solder mask at least partially surrounds, but does not substantially cover, the bonding pad. The solder ball pad also has an anchor pad coupled to the bonding pad and extending between the substrate and the solder mask.

Abstract: A microelectronics package comprising: a die, a lead frame comprising: a substrate having a first side and a second side, an array of contacts positioned on the first side and the second side, and an aperture extending through the substrate between the contacts, wherein at least one contact is electrically coupled to the die, and a mold compound encapsulating the die and the substrate.

Abstract: A method, comprising bonding a first wire to a single die bond pad to form a first bond, bonding the first wire to a bond post to form a second bond, bonding a second wire to the first bond, and coupling the second wire to the bond post.

Abstract: A semiconductor die has three rows or more of bond pads with minimum pitch. The die is mounted on a package substrate having three rows or more of bond fingers and/or conductive rings. The bond pads on the outermost part of the die (nearest the perimeter of the die) are connected by a relatively lower height wire achieved by reverse stitching to the innermost ring(s) or row (farthest from the perimeter of the package substrate) of bond fingers. The innermost row of bond pads is connected by a relatively higher height wire achieved by ball bond to wedge bond to the outermost row of the bond fingers. The intermediate row of bond pads is connected by relatively intermediate height wire by ball bond to wedge bond to the intermediate row of bond fingers. The varying height wire allows for tightly packed bond pads. The structure is adaptable for stacked die.

Abstract: A multi-chip assembly (100) uses a clip (110) to retain multiple integrated circuits (124-130) to an assembly substrate (140). The use of a thermal medium between the integrated circuits and the heat sinks (120, 122) allows the assembly to be disassembled for rework purposes. The clip contains edge clamps (112), alignment rails (114), and alignment features (116, 316, 416) to properly orient the clip, heat sink, integrated circuits, and assembly substrate.