Abstract: Systems and methods are provided for fast cyclic redundancy check code generation. For example, a method includes representing the sequence of bits as a polynomial over a Galois field base 2; partitioning the polynomial into a plurality of partial polynomials, wherein the polynomial equals the sum of the partial polynomials; concurrently generating a respective partial CRC code for each of the partial polynomials; weighting each partial CRC code according to a position of the respective partial polynomial in the polynomial; and summing the weighted partial CRC codes.

Abstract: Systems and methods are provided for fast cyclic redundancy check code generation. For example, a method includes representing the sequence of bits as a polynomial over a Galois field base 2; partitioning the polynomial into a plurality of partial polynomials, wherein the polynomial equals the sum of the partial polynomials; concurrently generating a respective partial CRC code for each of the partial polynomials; weighting each partial CRC code according to a position of the respective partial polynomial in the polynomial; and summing the weighted partial CRC codes.

Abstract: Example implementations relate to a bridge port extender. For example, a bridge port extender may include a processor. The processor may receive an Ethernet frame from a network bridge, where the Ethernet frame includes an encapsulated portion and an unencapsulated portion, and where the unencapsulated portion includes an E-tag. The processor may remove the E-tag from the unencapsulated portion to form a modified Ethernet frame. The processor may transmit the modified Ethernet frame to a client device based on the E-tag.

Abstract: Example implementations relate to a bridge port extender. For example, a bridge port extender may include a processor. The processor may receive an Ethernet frame from a network bridge, where the Ethernet frame includes an encapsulated portion and an unencapsulated portion, and where the unencapsulated portion includes an E-tag. The processor may remove the E-tag from the unencapsulated portion to form a modified Ethernet frame. The processor may transmit the modified Ethernet frame to a client device based on the E-tag.

Abstract: A forward counter block may include at least one of a plurality of local counter storage elements for counting events. The forward counter block may also include an update engine, the update engine configured to update an external memory by forwarding a value stored in any of said at lease one of a plurality of local counter storage elements and return a zero value to that local counter storage element, when the value stored in that local counter storage element reaches or surpasses a threshold value.

Abstract: One example includes a network device. The network device includes a queue to receive frames from a source, a processor, and a memory coupled to the processor. The memory stores instructions causing the processor, after execution of the instructions by the processor, to deposit tokens into a first token bucket at a first rate, determine whether a frame length of a frame received by the queue is less than the tokens in the first token bucket, remove tokens from the first token bucket in response to the frame length being less than the tokens in the first token bucket, and generate a congestion notification message in response to the frame length not being less than the tokens in the first token bucket. Each token represents a unit of bytes of a predetermined size.

Abstract: One example provides a network device including a queue to receive in profile frames and out of profile frames, a processor, and a memory communicatively coupled to the processor. The memory stores instructions causing the processor, after execution of the instructions by the processor, to determine whether a predetermined operating point of the queue has been exceeded, and in response to determining that the predetermined operating point of the queue has been exceeded, forward the in profile frames, sample the out of profile frames, and generate a congestion notification message for each sampled out of profile frame to be sent to a source of the out of profile frames to reduce the transmission rate of frames.

Abstract: Example embodiments disclosed herein relate to passing or forwarding a frame. A frame is received from a first device. The frame includes a first header including a destination Media Access Control (MAC) address followed by a second header including a source MAC address followed by a third header including an Ethertype. The frame is passed or forwarded to a second device based on the Ethertype.

Abstract: One example includes a network device. The network device includes a plurality of ports and application specific logic. The application specific logic is to receive a multicast packet including client data and a header, the header including a route group identifier. The application specific logic is to determine a group of routed interfaces and an associated set of ports for each routed interface based on the route group identifier. The application specific logic is to replicate the client data to provide a packet for each routed interface and transmit, for each routed interface, the packet for the routed interface to the associated set of ports for the routed interface.

Abstract: A forward counter block may include at least one of a plurality of local counter storage elements for counting events. The forward counter block may also include an update engine, the update engine configured to update an external memory by forwarding a value stored in any of said at lease one of a plurality of local counter storage elements and return a zero value to that local counter storage element, when the value stored in that local counter storage element reaches or surpasses a threshold value.

Abstract: One embodiment disclosed relates to an integrated circuit including on-chip logic analyzer circuitry. The on-chip logic analyzer circuitry includes a triggering circuit configured to receive a source data signal and start/stop timing signals. The on-chip logic analyzer circuitry further includes a compression circuit configured to receive an uncompressed data signal from the triggering circuit and to perform compression so as to form a compressed data signal. Other embodiments, aspects and features are also disclosed.

Abstract: One embodiment disclosed relates to an integrated circuit including on-chip logic analyzer circuitry. The on-chip logic analyzer circuitry includes a triggering circuit configured to receive a source data signal and start/stop timing signals. The on-chip logic analyzer circuitry further includes a compression circuit configured to receive an uncompressed data signal from the triggering circuit and to perform compression so as to form a compressed data signal. Other embodiments, aspects and features are also disclosed.