Abstract: Adjacent interconnect features are in staggered, vertically spaced positions, which accordingly reduces their capacitive coupling within a level of interconnect metallization. Adjacent interconnect features may comprise a plurality of first interconnect lines with spaces therebetween. A dielectric material is over the first interconnect lines and within the spaces between the first interconnect lines. Resultant topography in the dielectric material defines a plurality of trenches between the first interconnect lines. The adjacent interconnect features further comprise a plurality of second interconnect lines interdigitated with the first interconnect lines that occupy at least a portion of the trenches between individual ones of the first interconnect lines.

Abstract: Embodiments disclosed herein include interconnect layers that include non-uniform interconnect heights and methods of forming such devices. In an embodiment, an interconnect layer comprises an interlayer dielectric (ILD), a first interconnect disposed in the ILD, wherein the first interconnect has a first height, and a second interconnect disposed in the ILD, wherein the second interconnect has a second height that is different than the first height.

Abstract: A system can form a part in an initial geometry into a desired geometry. The system may include a roller tool and a robot arm that: (a) presses the roller tool onto a surface of the part and (b) moves the pressed roller tool along the surface of the part to form the desired geometry. The roller tool includes a ball and a support with a socket that receives the ball and enables the ball to rotate in the socket. The support may include a channel configured to carry fluid through the support toward the ball or away from the ball. The socket may deform such that contact area of the ball with the socket increases in response to the ball being pressed onto the surface above a threshold pressure.

Abstract: Methods, apparatuses, and systems for making prepregs are disclosed. A method may include depositing a resin material onto a surface of a fiber bed and forming a number of discrete resin regions thereon. A distance between the resin regions may be measured to provide desired exposed portions of the surface to facilitate permeation of air through the exposed portions of the surface in a direction perpendicular to a plane of the fiber bed during a curing process of the prepreg.

Abstract: Through-thickness permeable prepregs comprise a fiber bed and a plurality of discrete resin regions on a surface of the fiber bed separated by exposed fiber bed surface regions. Prepreg assemblies for processing such prepregs comprise an air permeable resin barrier material disposed over a surface of the prepreg opposite a forming tool. The air permeable resin barrier material is permeable to air or gas passing from the prepreg and is impermeable to resin passing from the prepreg. During processing, the prepreg assembly is subjected to a vacuum and elevated temperature to cure the resin and form a composite part. During processing, the air permeable resin barrier material prevents unwanted resin bleed from the prepreg, causing resin pressure in the prepreg to be maintained that reduces or eliminates unwanted formation or growth of internal voids to provide a composite part having a reduced degree of internal voids and pores.

Abstract: Methods, apparatuses, and systems for making prepregs are disclosed. A method may include depositing a resin material onto a surface of a fiber bed and forming a number of discrete resin regions thereon. A distance between the resin regions may be measured to provide desired exposed portions of the surface to facilitate permeation of air through the exposed portions of the surface in a direction perpendicular to a plane of the fiber bed during a curing process of the prepreg.

Abstract: Techniques and mechanisms for an integrated clock gate (ICG) to selectively output a clock signal, and to provide frequency division functionality. In an embodiment, an ICG circuit comprises first circuitry which is coupled to receive a first clock signal, and second circuitry which is coupled to receive a control signal. The first circuitry provides a single edge triggered flip-flop functionality, and is coupled to communicate a feedback signal which the first circuitry is further coupled to receive. Based on the control signal and the feedback signal, the second circuitry performs an exclusive OR (XOR) operation to selectively enable the first circuitry to generate a second clock signal based on the first clock signal. In another embodiment, a frequency of the second clock signal is substantially equal to one half of a frequency of the first clock signal.

Abstract: Adjacent interconnect features are in staggered, vertically spaced positions, which accordingly reduces their capacitive coupling within a level of interconnect metallization. Adjacent interconnect features may comprise a plurality of first interconnect lines with spaces therebetween. A dielectric material is over the first interconnect lines and within the spaces between the first interconnect lines. Resultant topography in the dielectric material defines a plurality of trenches between the first interconnect lines. The adjacent interconnect features further comprise a plurality of second interconnect lines interdigitated with the first interconnect lines that occupy at least a portion of the trenches between individual ones of the first interconnect lines.

Abstract: A fused dot-product multiply-accumulate (MAC) circuit may support variable precisions of floating-point data elements to perform computations (e.g., MAC operations) in deep learning operations. An operation mode of the circuit may be selected based on the precision of an input element. The operation mode may be a FP16 mode or a FP8 mode. In the FP8 mode, product exponents may be computed based on exponents of floating-point input elements. A maximum exponent may be selected from the one or more product exponents. A global maximum exponent may be selected from a plurality of maximum exponents. A product mantissa may be computed and aligned with another product mantissa based on a difference between the global maximum exponent and a corresponding maximum exponent. An adder tree may accumulate the aligned product mantissas and compute a partial sum mantissa. The partial sum mantissa may be normalized using the global maximum exponent.

Abstract: Methods, apparatuses, and systems for making prepregs are disclosed. A method may include depositing a resin material onto a surface of a fiber bed and forming a number of discrete resin regions thereon. A distance between the resin regions may be measured to provide desired exposed portions of the surface to facilitate permeation of air through the exposed portions of the surface in a direction perpendicular to a plane of the fiber bed during a curing process of the prepreg.

Abstract: Projectile loading systems for toy launchers that discharge soft spherical, but tacky, projectiles, the loading systems including a projectile hopper for storing the projectiles, a chute at the bottom of the hopper, the chute having a central groove for lining the projectiles in a single file, an agitator in the hopper. Arrangements of projectile launcher and accessories, container apparatus and the like are provided in differing sizes and orientations with aesthetics of rails in unique angled offset orientations for functions configured with attachment types, bottles, containers, and other apparatus in various combinations.

Abstract: Methods, apparatuses, and systems for making prepregs are disclosed. A method may include depositing a resin material onto a surface of a fiber bed and forming a number of discrete resin regions thereon. A distance between the resin regions may be measured to provide desired exposed portions of the surface to facilitate permeation of air through the exposed portions of the surface in a direction perpendicular to a plane of the fiber bed during a curing process of the prepreg.

Abstract: Projectile loading systems for toy launchers that discharge soft spherical, but tacky, projectiles, the loading systems including a projectile hopper for storing the projectiles, a chute at the bottom of the hopper, the chute having a central groove for lining the projectiles in a single file, an agitator in the hopper for disturbing the tacky projectiles in the hopper to separate them, and a projectile transfer structure for carrying a projectile, one at a time, from the chute to a breech or from a feed track during respective priming cycles.

Abstract: Systems, apparatuses and methods may provide for technology that conduct a first alignment between a plurality of floating-point numbers based on a first subset of exponent bits. The technology may also conduct, at least partially in parallel with the first alignment, a second alignment between the plurality of floating-point numbers based on a second subset of exponent bits, where the first subset of exponent bits are LSBs and the second subset of exponent bits are MSBs. In one example, technology adds the aligned plurality of floating-point numbers to one another. With regard to the second alignment, the technology may also identify individual exponents of a plurality of floating-point numbers, identify a maximum exponent across the individual exponents, and conduct a subtraction of the individual exponents from the maximum exponent, where the subtraction is conducted from MSB to LSB.

Abstract: Methods, apparatuses, and systems for making prepregs are disclosed. A method may include depositing a resin material onto a surface of a fiber bed and forming a number of discrete resin regions thereon. A distance between the resin regions may be measured to provide desired exposed portions of the surface to facilitate permeation of air through the exposed portions of the surface in a direction perpendicular to a plane of the fiber bed during a curing process of the prepreg.

Abstract: Projectile loading systems for toy launchers that discharge soft spherical, but tacky, projectiles, the loading systems including a projectile hopper for storing the projectiles, a chute at the bottom of the hopper, the chute having a central groove for lining the projectiles in a single file, an agitator in the hopper for disturbing the tacky projectiles in the hopper to separate them, and a projectile transfer structure for carrying a projectile, one at a time, from the chute to a breech or from a feed track during respective priming cycles.

Abstract: Embodiments disclosed herein include a semiconductor device with interconnects with non-uniform heights. In an embodiment, the semiconductor device comprises a semiconductor substrate, and a back end of line (BEOL) stack over the semiconductor substrate. In an embodiment, the BEOL stack comprises first interconnects and second interconnects in an interconnect layer of the BEOL stack. In an embodiment, the first interconnects have a first height and the second interconnects have a second height that is different than the first height.

Abstract: Embodiments disclosed herein include interconnect layers that include non-uniform interconnect heights and methods of forming such devices. In an embodiment, an interconnect layer comprises an interlayer dielectric (ILD), a first interconnect disposed in the ILD, wherein the first interconnect has a first height, and a second interconnect disposed in the ILD, wherein the second interconnect has a second height that is different than the first height.

Abstract: A configurable integrated circuit to compute vector dot products between a first N-bit vector and a second N-bit vector in a plurality of precision modes. An embodiment includes M slices, each of which calculates the vector dot products between a corresponding segment of the first and the second N-bit vectors. Each of the slices outputs intermediary multiplier results for the lower precision modes, but not for highest precision mode. A plurality of adder trees to sum up the plurality of intermediate multiplier results, with each adder tree producing a respective adder out result. An accumulator to merge the adder out result from a first adder tree with the adder out result from a second adder tree to produce the vector dot product of the first and the second N-bit vector in the highest precision mode.

Abstract: Systems, apparatuses and methods may provide for technology that conduct a first alignment between a plurality of floating-point numbers based on a first subset of exponent bits. The technology may also conduct, at least partially in parallel with the first alignment, a second alignment between the plurality of floating-point numbers based on a second subset of exponent bits, where the first subset of exponent bits are LSBs and the second subset of exponent bits are MSBs. In one example, technology adds the aligned plurality of floating-point numbers to one another. With regard to the second alignment, the technology may also identify individual exponents of a plurality of floating-point numbers, identify a maximum exponent across the individual exponents, and conduct a subtraction of the individual exponents from the maximum exponent, where the subtraction is conducted from MSB to LSB.