Abstract: A system can form a part in an initial geometry into a desired geometry. The system may include a roller tool and a robot arm that: (a) presses the roller tool onto a surface of the part and (b) moves the pressed roller tool along the surface of the part to form the desired geometry. The roller tool includes a ball and a support with a socket that receives the ball and enables the ball to rotate in the socket. The support may include a channel configured to carry fluid through the support toward the ball or away from the ball. The socket may deform such that contact area of the ball with the socket increases in response to the ball being pressed onto the surface above a threshold pressure.

Abstract: Methods, apparatuses, and systems for making prepregs are disclosed. A method may include depositing a resin material onto a surface of a fiber bed and forming a number of discrete resin regions thereon. A distance between the resin regions may be measured to provide desired exposed portions of the surface to facilitate permeation of air through the exposed portions of the surface in a direction perpendicular to a plane of the fiber bed during a curing process of the prepreg.

Abstract: One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute a 32-bit intermediate product of 16-bit operands and to compute a 32-bit sum based on the 32-bit intermediate product.

Abstract: One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute an intermediate product of 16-bit operands and to compute a 32-bit sum based on the intermediate product.

Abstract: Through-thickness permeable prepregs comprise a fiber bed and a plurality of discrete resin regions on a surface of the fiber bed separated by exposed fiber bed surface regions. Prepreg assemblies for processing such prepregs comprise an air permeable resin barrier material disposed over a surface of the prepreg opposite a forming tool. The air permeable resin barrier material is permeable to air or gas passing from the prepreg and is impermeable to resin passing from the prepreg. During processing, the prepreg assembly is subjected to a vacuum and elevated temperature to cure the resin and form a composite part. During processing, the air permeable resin barrier material prevents unwanted resin bleed from the prepreg, causing resin pressure in the prepreg to be maintained that reduces or eliminates unwanted formation or growth of internal voids to provide a composite part having a reduced degree of internal voids and pores.

Abstract: One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute a 32-bit intermediate product of 16-bit operands and to compute a 32-bit sum based on the 32-bit intermediate product.

Abstract: An apparatus includes a plurality of delay generators, a first plurality of flip-flop circuits, a second plurality of flip-flop circuits, and a third plurality of flip-flop circuits. The plurality of delay generators includes a data delay generator, an enable delay generator, and a reference delay generator. The first plurality of flip-flop circuits is coupled to the data delay generator to receive a delayed data input signal, and provide the delayed data input signal to a plurality of data input terminals of a memory circuit. The second plurality of flip-flop circuits is coupled to the enable delay generator to receive a delayed enable signal and provide the delayed enable signal to a plurality of enable terminals of the memory circuit. The third plurality of flip-flop circuits is coupled to an output terminal of the memory circuit. The reference delay generator provides a synchronized clock signal to the flip-flop circuits.

Abstract: Methods, apparatuses, and systems for making prepregs are disclosed. A method may include depositing a resin material onto a surface of a fiber bed and forming a number of discrete resin regions thereon. A distance between the resin regions may be measured to provide desired exposed portions of the surface to facilitate permeation of air through the exposed portions of the surface in a direction perpendicular to a plane of the fiber bed during a curing process of the prepreg.

Abstract: One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute an intermediate product of 16-bit operands and to compute a 32-bit sum based on the intermediate product.

Abstract: An apparatus includes a first port set that includes an input port and an output port. The apparatus further includes a plurality of second port sets. Each of the second port sets includes an input port coupled to the output port of the first port set and an output port coupled to the input port of the first port set. The plurality of second port sets are to each communicate at a first maximum bandwidth and the first port set is to communicate at a second maximum bandwidth that is higher than the first maximum bandwidth.

Abstract: Embodiments herein relate to a pulse generator which provides first and second clock pulses to one or more pulsed latches, where the pulse generator replicates a delay of the pulsed latches in providing the first and second clock pulses. The pulse generator can include a replica of latch components in the pulsed latches such as a tri-state inverter, a transmission gate and inverters, where an output of the tri-state inverter is coupled to the transmission gate and to an input of the inverter, and an output of the inverter is coupled to an input of the tri-state inverter. The tri-state inverter can be a modified tri-state inverter with an output forced to “1” when a clock signal is “0.” In one approach, the latch components of the pulse generator are to write a logic 1 when a clock signal goes high.

Abstract: One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute an intermediate product of 16-bit operands and to compute a 32-bit sum based on the intermediate product.

Abstract: Certain aspects of the present disclosure provide techniques for providing an augmented reality user interface, including: receiving, by an image sensor of an electronic device, an image of a physical document; determining a document type associated with the physical document by performing image recognition on the image of the physical document; determining an augmented reality template to display on a display of the electronic device; displaying the augmented reality template on the display of the electronic device, wherein the augmented reality template is aligned in three dimensions with the physical document; determining a distance between the physical document and the electronic device; and enabling one or more interactive user interface elements within the augmented reality template displayed on the display of the electronic device if the determined distance between the physical document and the electronic device is less than a threshold distance.

Abstract: Certain aspects of the present disclosure provide techniques for providing an augmented reality user interface, including: receiving, by an image sensor of an electronic device, an image of a physical document; determining a document type associated with the physical document by performing image recognition on the image of the physical document; determining an augmented reality template to display on a display of the electronic device; displaying the augmented reality template on the display of the electronic device, wherein the augmented reality template is aligned in three dimensions with the physical document; determining a distance between the physical document and the electronic device; and enabling one or more interactive user interface elements within the augmented reality template displayed on the display of the electronic device if the determined distance between the physical document and the electronic device is less than a threshold distance.

Abstract: An apparatus includes a first port set that includes an input port and an output port. The apparatus further includes a plurality of second port sets. Each of the second port sets includes an input port coupled to the output port of the first port set and an output port coupled to the input port of the first port set. The plurality of second port sets are to each communicate at a first maximum bandwidth and the first port set is to communicate at a second maximum bandwidth that is higher than the first maximum bandwidth.

Abstract: Techniques and mechanisms for an integrated clock gate (ICG) to selectively output a clock signal, and to provide frequency division functionality. In an embodiment, an ICG circuit comprises first circuitry which is coupled to receive a first clock signal, and second circuitry which is coupled to receive a control signal. The first circuitry provides a single edge triggered flip-flop functionality, and is coupled to communicate a feedback signal which the first circuitry is further coupled to receive. Based on the control signal and the feedback signal, the second circuitry performs an exclusive OR (XOR) operation to selectively enable the first circuitry to generate a second clock signal based on the first clock signal. In another embodiment, a frequency of the second clock signal is substantially equal to one half of a frequency of the first clock signal.

Abstract: Adjacent interconnect features are in staggered, vertically spaced positions, which accordingly reduces their capacitive coupling within a level of interconnect metallization. Adjacent interconnect features may comprise a plurality of first interconnect lines with spaces therebetween. A dielectric material is over the first interconnect lines and within the spaces between the first interconnect lines. Resultant topography in the dielectric material defines a plurality of trenches between the first interconnect lines. The adjacent interconnect features further comprise a plurality of second interconnect lines interdigitated with the first interconnect lines that occupy at least a portion of the trenches between individual ones of the first interconnect lines.

Abstract: A fused dot-product multiply-accumulate (MAC) circuit may support variable precisions of floating-point data elements to perform computations (e.g., MAC operations) in deep learning operations. An operation mode of the circuit may be selected based on the precision of an input element. The operation mode may be a FP16 mode or a FP8 mode. In the FP8 mode, product exponents may be computed based on exponents of floating-point input elements. A maximum exponent may be selected from the one or more product exponents. A global maximum exponent may be selected from a plurality of maximum exponents. A product mantissa may be computed and aligned with another product mantissa based on a difference between the global maximum exponent and a corresponding maximum exponent. An adder tree may accumulate the aligned product mantissas and compute a partial sum mantissa. The partial sum mantissa may be normalized using the global maximum exponent.

Abstract: Methods, apparatuses, and systems for making prepregs are disclosed. A method may include depositing a resin material onto a surface of a fiber bed and forming a number of discrete resin regions thereon. A distance between the resin regions may be measured to provide desired exposed portions of the surface to facilitate permeation of air through the exposed portions of the surface in a direction perpendicular to a plane of the fiber bed during a curing process of the prepreg.

Abstract: One embodiment provides a graphics processor comprising a memory controller and a graphics processing resource coupled with the memory controller. The graphics processing resource includes circuitry configured to execute an instruction to perform a matrix operation on first input including weight data and second input including input activation data, generate intermediate data based on a result of the matrix operation, quantize the intermediate data to a floating-point format determined based on a statistical distribution of first output data, and output, as second output data, quantized intermediate data in a determined floating-point format.