Patents by Inventor Mark Anders
Mark Anders has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11899908Abstract: Certain aspects of the present disclosure provide techniques for providing an augmented reality user interface, including: receiving, by an image sensor of an electronic device, an image of a physical document; determining a document type associated with the physical document by performing image recognition on the image of the physical document; determining an augmented reality template to display on a display of the electronic device; displaying the augmented reality template on the display of the electronic device, wherein the augmented reality template is aligned in three dimensions with the physical document; determining a distance between the physical document and the electronic device; and enabling one or more interactive user interface elements within the augmented reality template displayed on the display of the electronic device if the determined distance between the physical document and the electronic device is less than a threshold distance.Type: GrantFiled: September 26, 2022Date of Patent: February 13, 2024Assignee: Intuit, Inc.Inventors: Molly Beth Davis, Timothy Joseph Mueller, Mark Anders Holmberg, Jessica Jaiyeon Cho, Anoop Pratap Singh Tomar
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Patent number: 11868296Abstract: An apparatus includes a first port set that includes an input port and an output port. The apparatus further includes a plurality of second port sets. Each of the second port sets includes an input port coupled to the output port of the first port set and an output port coupled to the input port of the first port set. The plurality of second port sets are to each communicate at a first maximum bandwidth and the first port set is to communicate at a second maximum bandwidth that is higher than the first maximum bandwidth.Type: GrantFiled: March 22, 2022Date of Patent: January 9, 2024Assignee: Intel CorporationInventors: Himanshu Kaul, Mark A. Anders, Gregory K. Chen
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Publication number: 20240007087Abstract: Techniques and mechanisms for an integrated clock gate (ICG) to selectively output a clock signal, and to provide frequency division functionality. In an embodiment, an ICG circuit comprises first circuitry which is coupled to receive a first clock signal, and second circuitry which is coupled to receive a control signal. The first circuitry provides a single edge triggered flip-flop functionality, and is coupled to communicate a feedback signal which the first circuitry is further coupled to receive. Based on the control signal and the feedback signal, the second circuitry performs an exclusive OR (XOR) operation to selectively enable the first circuitry to generate a second clock signal based on the first clock signal. In another embodiment, a frequency of the second clock signal is substantially equal to one half of a frequency of the first clock signal.Type: ApplicationFiled: July 1, 2022Publication date: January 4, 2024Applicant: Intel CorporationInventors: Steven Hsu, Amit Agarwal, Simeon Realov, Mark Anders, Ram Krishnamurthy
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Publication number: 20230395506Abstract: Adjacent interconnect features are in staggered, vertically spaced positions, which accordingly reduces their capacitive coupling within a level of interconnect metallization. Adjacent interconnect features may comprise a plurality of first interconnect lines with spaces therebetween. A dielectric material is over the first interconnect lines and within the spaces between the first interconnect lines. Resultant topography in the dielectric material defines a plurality of trenches between the first interconnect lines. The adjacent interconnect features further comprise a plurality of second interconnect lines interdigitated with the first interconnect lines that occupy at least a portion of the trenches between individual ones of the first interconnect lines.Type: ApplicationFiled: June 6, 2022Publication date: December 7, 2023Applicant: Intel CorporationInventors: Miriam Reshotko, Elijah Karpov, Mark Anders, Gauri Auluck, Shakuntala Sundararajan, Michael Makowski, Caleb Barrett
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Publication number: 20230376274Abstract: A fused dot-product multiply-accumulate (MAC) circuit may support variable precisions of floating-point data elements to perform computations (e.g., MAC operations) in deep learning operations. An operation mode of the circuit may be selected based on the precision of an input element. The operation mode may be a FP16 mode or a FP8 mode. In the FP8 mode, product exponents may be computed based on exponents of floating-point input elements. A maximum exponent may be selected from the one or more product exponents. A global maximum exponent may be selected from a plurality of maximum exponents. A product mantissa may be computed and aligned with another product mantissa based on a difference between the global maximum exponent and a corresponding maximum exponent. An adder tree may accumulate the aligned product mantissas and compute a partial sum mantissa. The partial sum mantissa may be normalized using the global maximum exponent.Type: ApplicationFiled: July 31, 2023Publication date: November 23, 2023Applicant: Intel CorporationInventors: Mark Anders, Arnab Raha, Amit Agarwal, Steven Hsu, Deepak Abraham Mathaikutty, Ram K. Krishnamurthy, Martin Power
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Patent number: 11794377Abstract: Methods, apparatuses, and systems for making prepregs are disclosed. A method may include depositing a resin material onto a surface of a fiber bed and forming a number of discrete resin regions thereon. A distance between the resin regions may be measured to provide desired exposed portions of the surface to facilitate permeation of air through the exposed portions of the surface in a direction perpendicular to a plane of the fiber bed during a curing process of the prepreg.Type: GrantFiled: January 4, 2022Date of Patent: October 24, 2023Assignee: University of Southern CaliforniaInventors: Steven Nutt, Lessa Grunenfelder, Timotei Centea, Mark Anders, William Thomas Edwards, Sarah Grace Katz Schechter
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Patent number: 11720355Abstract: One embodiment provides a graphics processor comprising a memory controller and a graphics processing resource coupled with the memory controller. The graphics processing resource includes circuitry configured to execute an instruction to perform a matrix operation on first input including weight data and second input including input activation data, generate intermediate data based on a result of the matrix operation, quantize the intermediate data to a floating-point format determined based on a statistical distribution of first output data, and output, as second output data, quantized intermediate data in a determined floating-point format.Type: GrantFiled: June 7, 2022Date of Patent: August 8, 2023Assignee: Intel CorporationInventors: Himanshu Kaul, Mark A. Anders, Sanu K. Mathew, Anbang Yao, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Tatiana Shpeisman, Abhishek R. Appu, Altug Koker, Kamal Sinha, Balaji Vembu, Nicolas C. Galoppo Von Borries, Eriko Nurvitadhi, Rajkishore Barik, Tsung-Han Lin, Vasanth Ranganathan, Sanjeev Jahagirdar
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Publication number: 20230046506Abstract: One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute an intermediate product of 16-bit operands and to compute a 32-bit sum based on the intermediate product.Type: ApplicationFiled: October 17, 2022Publication date: February 16, 2023Applicant: Intel CorporationInventors: Himanshu Kaul, Mark A. Anders, Sanu K. Mathew, Anbang Yao, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Tatiana Shpeisman, Abhishek R. Appu, Altug Koker, Kamal Sinha, Balaji Vembu, Nicolas C. Galoppo Von Borries, Eriko Nurvitadhi, Rajkishore Barik, Tsung-Han Lin, Vasanth Ranganathan, Sanjeev Jahagirdar
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Publication number: 20230012805Abstract: Certain aspects of the present disclosure provide techniques for providing an augmented reality user interface, including: receiving, by an image sensor of an electronic device, an image of a physical document; determining a document type associated with the physical document by performing image recognition on the image of the physical document; determining an augmented reality template to display on a display of the electronic device; displaying the augmented reality template on the display of the electronic device, wherein the augmented reality template is aligned in three dimensions with the physical document; determining a distance between the physical document and the electronic device; and enabling one or more interactive user interface elements within the augmented reality template displayed on the display of the electronic device if the determined distance between the physical document and the electronic device is less than a threshold distance.Type: ApplicationFiled: September 26, 2022Publication date: January 19, 2023Inventors: Molly Beth DAVIS, Timothy Joseph MUELLER, Mark Anders HOLMBERG, Jessica Jaiyeon CHO, Anoop Pratap Singh TOMAR
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Publication number: 20220357945Abstract: One embodiment provides a graphics processor comprising a memory controller and a graphics processing resource coupled with the memory controller. The graphics processing resource includes circuitry configured to execute an instruction to perform a matrix operation on first input including weight data and second input including input activation data, generate intermediate data based on a result of the matrix operation, quantize the intermediate data to a floating-point format determined based on a statistical distribution of first output data, and output, as second output data, quantized intermediate data in a determined floating-point format.Type: ApplicationFiled: June 7, 2022Publication date: November 10, 2022Applicant: Intel CorporationInventors: Himanshu Kaul, Mark A. Anders, Sanu K. Mathew, Anbang Yao, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Tatiana Shpeisman, Abhishek R. Appu, Altug Koker, Kamal Sinha, Balaji Vembu, Nicolas C. Galoppo Von Borries, Eriko Nurvitadhi, Rajkishore Barik, Tsung-Han Lin, Vasanth Ranganathan, Sanjeev Jahagirdar
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Patent number: 11494051Abstract: Certain aspects of the present disclosure provide techniques for providing an augmented reality user interface, including: receiving, by an image sensor of an electronic device, an image of a physical document; determining a document type associated with the physical document by performing image recognition on the image of the physical document; determining an augmented reality template to display on a display of the electronic device; displaying the augmented reality template on the display of the electronic device, wherein the augmented reality template is aligned in three dimensions with the physical document; determining a distance between the physical document and the electronic device; and enabling one or more interactive user interface elements within the augmented reality template displayed on the display of the electronic device if the determined distance between the physical document and the electronic device is less than a threshold distance.Type: GrantFiled: November 1, 2018Date of Patent: November 8, 2022Assignee: INTUIT, INC.Inventors: Molly Beth Davis, Timothy Joseph Mueller, Mark Anders Holmberg, Jessica Jaiyeon Cho, Anoop Pratap Singh Tomar
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Publication number: 20220282943Abstract: Projectile loading systems for toy launchers that discharge soft spherical, but tacky, projectiles, the loading systems including a projectile hopper for storing the projectiles, a chute at the bottom of the hopper, the chute having a central groove for lining the projectiles in a single file, an agitator in the hopper. Arrangements of projectile launcher and accessories, container apparatus and the like are provided in differing sizes and orientations with aesthetics of rails in unique angled offset orientations for functions configured with attachment types, bottles, containers, and other apparatus in various combinations.Type: ApplicationFiled: March 23, 2022Publication date: September 8, 2022Applicant: Hasbro, Inc.Inventors: Robert J. DeRoche, Robert C. Maschin, Mark Anders
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Publication number: 20220226016Abstract: A system can include an elongated member that includes a proximal portion and a distal portion that includes an agitator. The elongated member can extend through a working channel of an endoscope placed within a patient such that the agitator extends past a distal end of the endoscope into a target region within the patient. The agitator can include a plurality of disruption elements that can be in a low-profile state when within the working channel of the endoscope and can transition to an expanded state when advanced past the distal end of the endoscope. The plurality of disruption elements can define an empty cage configuration when in the expanded state. The system can include a driver coupled to the proximal portion of the elongated member. The driver can rotate the elongated member about a longitudinal axis of the elongated member.Type: ApplicationFiled: March 23, 2022Publication date: July 21, 2022Inventors: Robert A. Ganz, Mark Anders Rydell, Travis Sessions, Steven Berhow, Doug Wahnschaffe, Michael W. Augustine
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Publication number: 20220214988Abstract: An apparatus includes a first port set that includes an input port and an output port. The apparatus further includes a plurality of second port sets. Each of the second port sets includes an input port coupled to the output port of the first port set and an output port coupled to the input port of the first port set. The plurality of second port sets are to each communicate at a first maximum bandwidth and the first port set is to communicate at a second maximum bandwidth that is higher than the first maximum bandwidth.Type: ApplicationFiled: March 22, 2022Publication date: July 7, 2022Applicant: Intel CorporationInventors: Himanshu Kaul, Mark A. Anders, Gregory K. Chen
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Publication number: 20220203576Abstract: Methods, apparatuses, and systems for making prepregs are disclosed. A method may include depositing a resin material onto a surface of a fiber bed and forming a number of discrete resin regions thereon. A distance between the resin regions may be measured to provide desired exposed portions of the surface to facilitate permeation of air through the exposed portions of the surface in a direction perpendicular to a plane of the fiber bed during a curing process of the prepreg.Type: ApplicationFiled: January 4, 2022Publication date: June 30, 2022Inventors: Steven Nutt, Lessa Grunenfelder, Timotei Centea, Mark Anders, William Thomas Edwards, Sarah Grace Katz Schechter
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Publication number: 20220188075Abstract: A FPMAC operation has two operands: an input operand and a weight operand. The operands may have a format of FP16, BF16, or INT8. Each operand is split into two portions. The two portions are stored in separate storage units. Then operands are transferred to register files of a PE, with each register file storing bits of an operand sequentially. The PE performs the FPMAC operation based on the operands. The PE may include an FPMAC unit configured to compute an individual partial sum of the PE. The PE may also include an FP adder to accumulate the individual partial sum with other data, such as an output from another PE or an output form another PE array. The FP adder may be fused with the FPMAC unit in a single circuit that can do speculative alignment and has separate critical paths for alignment and normalization.Type: ApplicationFiled: March 7, 2022Publication date: June 16, 2022Applicant: Intel CorporationInventors: Arnab Raha, Mark A. Anders, Raymond Jit-Hung Sung, Debabrata Mohapatra, Deepak Abraham Mathaikutty, Ram K. Krishnamurthy, Himanshu Kaul
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Patent number: 11360767Abstract: A processing apparatus is provided comprising a multiprocessor having a multithreaded architecture. The multiprocessor can execute at least one single instruction to perform parallel mixed precision matrix operations. In one embodiment the apparatus includes a memory interface and an array of multiprocessors coupled to the memory interface. At least one multiprocessor in the array of multiprocessors is configured to execute a fused multiply-add instruction in parallel across multiple threads.Type: GrantFiled: July 6, 2021Date of Patent: June 14, 2022Assignee: Intel CorporationInventors: Himanshu Kaul, Mark A. Anders, Sanu K. Mathew, Anbang Yao, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Tatiana Shpeisman, Abhishek R. Appu, Altug Koker, Kamal Sinha, Balaji Vembu, Nicolas C. Galoppo Von Borries, Eriko Nurvitadhi, Rajkishore Barik, Tsung-Han Lin, Vasanth Ranganathan, Sanjeev Jahagirdar
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Patent number: 11346624Abstract: Projectile loading systems for toy launchers that discharge soft spherical, but tacky, projectiles, the loading systems including a projectile hopper for storing the projectiles, a chute at the bottom of the hopper, the chute having a central groove for lining the projectiles in a single file, an agitator in the hopper for disturbing the tacky projectiles in the hopper to separate them, and a projectile transfer structure for carrying a projectile, one at a time, from the chute to a breech or from a feed track during respective priming cycles.Type: GrantFiled: October 6, 2020Date of Patent: May 31, 2022Assignee: Hasbro, Inc.Inventors: Robert J DeRoche, Robert C Maschin, Mark Anders
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Patent number: 11321263Abstract: An apparatus includes a first port set that includes an input port and an output port. The apparatus further includes a plurality of second port sets. Each of the second port sets includes an input port coupled to the output port of the first port set and an output port coupled to the input port of the first port set. The plurality of second port sets are to each communicate at a first maximum bandwidth and the first port set is to communicate at a second maximum bandwidth that is higher than the first maximum bandwidth.Type: GrantFiled: December 17, 2014Date of Patent: May 3, 2022Assignee: Intel CorporationInventors: Himanshu Kaul, Mark A. Anders, Gregory K. Chen
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Patent number: 11288040Abstract: Systems, apparatuses and methods may provide for technology that conduct a first alignment between a plurality of floating-point numbers based on a first subset of exponent bits. The technology may also conduct, at least partially in parallel with the first alignment, a second alignment between the plurality of floating-point numbers based on a second subset of exponent bits, where the first subset of exponent bits are LSBs and the second subset of exponent bits are MSBs. In one example, technology adds the aligned plurality of floating-point numbers to one another. With regard to the second alignment, the technology may also identify individual exponents of a plurality of floating-point numbers, identify a maximum exponent across the individual exponents, and conduct a subtraction of the individual exponents from the maximum exponent, where the subtraction is conducted from MSB to LSB.Type: GrantFiled: June 7, 2019Date of Patent: March 29, 2022Assignee: Intel CorporationInventors: Himanshu Kaul, Mark Anders