Abstract: A semiconductor device has a first surface contact provided on a first surface of the semiconductor device, a second surface contact provided on the first surface, physically separated from the first surface contact, a third surface contact provided on the first surface between the first surface contact and second surface contact and a first trench provided in the first surface and extending into the device from the first surface, and a conductive plug provided in the trench, The trench is located in an area of the first surface between an end of the third surface contact and an edge of the first surface. The first surface contact and the second surface contact overlie the first trench and the conductive plug in the first trench provides a conductive path between the first and second surface contacts.

Abstract: A semiconductor power device having an active region, the active region of the device including at least two split-gate trench regions, and the two laterally adjacent split-gate trench regions are separated by a mesa region, and two or more contact regions of a first conductivity type located in the mesa region. The contact regions of a first conductivity type are in contact with the two adjacent split-gate trench regions so that, in use, a channel is formed along a side of each split-gate trench region. The device further includes at least two insulating spacer regions located over and aligned with the two or more contact regions of a first conductivity type, and a source contact extending from an upper surface of the device within the mesa region and between the at least two insulating spacer regions.

Abstract: A semiconductor device and method of manufacturing the semiconductor device is disclosed. A layer of metallic material is deposited onto a substrate, the layer having a top surface. At least an edge area of the layer is masked with a first lithography mask and metallic material is removed from the edge area according to the first mask, whereby a first portion of the edge area has a thickness intermediate to the substrate and the layer top surface. The first portion of the edge area is masked with a second lithography mask and metallic material is removed from the first portion according to the second mask, whereby second portions of the edge area are free of deposited metallic material.

Abstract: A method of manufacturing a semiconductor device, such as a power MOSFET, including: forming a metal layer, the metal layer including an edge where the metal layer ends; forming a passivation layer at a layer higher than the metal layer; and forming a passivation slot in the passivation layer, the passivation slot is at least partially positioned over the metal layer, and the passivation slot divides the passivation layer into multiple regions, each region experiences a reduced tensile stress ?SiNx as a result of the passivation slot.

Abstract: A method of manufacturing a semiconductor device, such as a power MOSFET, including: forming a metal layer, the metal layer including an edge where the metal layer ends; forming a passivation layer at a layer higher than the metal layer; and forming a passivation slot in the passivation layer, the passivation slot is at least partially positioned over the metal layer, and the passivation slot divides the passivation layer into multiple regions, each region experiences a reduced tensile stress ?SiNx as a result of the passivation slot.

Abstract: A semiconductor arrangement comprising; a normally-on transistor having first and second main terminals and a control terminal, a normally-off transistor having first and second main terminals and a control terminal, the transistors connected in a cascode arrangement by a connection between one of the main terminals of the normally-on transistor and one of the main terminals of the normally-off transistor, a current-source arrangement connected to a node on the connection and configured to provide for control of the voltage at said node between the normally-on and normally-off transistors by providing for a predetermined current flow, wherein the semiconductor arrangement comprises a first semiconductor die of III-V semiconductor type having the normally-on transistor formed therein and a second semiconductor die having the normally-off transistor formed therein, the current-source arrangement formed in the first and/or second semiconductor dies.

Abstract: A semiconductor device and a method of making the same are disclosed. The device includes a substrate including an AlGaN layer located on a GaN layer for forming a two dimensional electron gas at an interface between the AlGaN layer and the GaN layer. The device also includes a plurality of electrical contacts located on a major surface of the substrate. The device further includes a plurality of passivation layers located on the major surface of the substrate. The plurality of passivation layers includes a first passivation layer of a first passivation material contacting a first area of the major surface and a second passivation layer of a second passivation material contacting a second area of the major surface. The first and second passivation materials are different passivation materials. The different passivation materials may be compositions of silicon nitride that include different proportions of silicon.

Abstract: A semiconductor arrangement comprising; a die of III-V semiconductor material; a resistor element integrated in the die, the resistor element comprising a track defined by a first implant material in the III-V semiconductor material of the die, said track electrically isolated from substantially the remainder of the die by an isolation region that surrounds the track.

Abstract: A semiconductor arrangement comprising; a die of III-V semiconductor material; a resistor element integrated in the die, the resistor element comprising a track defined by a first implant material in the III-V semiconductor material of the die, said track electrically isolated from substantially the remainder of the die by an isolation region that surrounds the track.

Abstract: A semiconductor arrangement comprising; a normally-on transistor having first and second main terminals and a control terminal, a normally-off transistor having first and second main terminals and a control terminal, the transistors connected in a cascade arrangement by a connection between one of the main terminals of the normally-on transistor and one of the main terminals of the normally-off transistor, a current-source arrangement connected to a node on the connection and configured to provide for control of the voltage at said node between the normally-on and normally-off transistors by providing for a predetermined current flow, wherein the semiconductor arrangement comprises a first semiconductor die of III-V semiconductor type having the normally-on transistor formed therein and a second semiconductor die having the normally-off transistor formed therein, the current-source arrangement formed in the first and/or second semiconductor dies.

Abstract: A semiconductor device and a method of making the same are disclosed. The device includes a substrate including an AlGaN layer located on a GaN layer for forming a two dimensional electron gas at an interface between the AlGaN layer and the GaN layer. The device also includes a plurality of electrical contacts located on a major surface of the substrate. The device further includes a plurality of passivation layers located on the major surface of the substrate. The plurality of passivation layers includes a first passivation layer of a first passivation material contacting a first area of the major surface and a second passivation layer of a second passivation material contacting a second area of the major surface. The first and second passivation materials are different passivation materials.