Abstract: A circuit at an interface between a device and an interconnect fabric is configured to track outstanding transactions associated with the device and ensure the completion of the outstanding transactions before rebooting or powering down the device. In some embodiments, the circuit is also configurable to provide appropriate responses when the device is powered down or is being rebooted such that other devices in the system can still operate even without knowing that the device is inactive and would not hang because no response is received from the device.

Abstract: Disclosed herein are techniques for tracking usage of a storage-class memory. In one embodiment, a method includes receiving a first statistics update entry and a second statistics update entry by a memory controller for a memory, and assembling the statistics update entries into a statistics log entry. The first statistics update entry indicates a number of operations performed on a first memory block in the memory, and the second statistics update entry indicates a number of operations performed on a second memory block in the memory. The method also includes determining a persistent memory region in a persistent memory for storing the statistics log entry, and writing the statistics log entry into the persistent memory region, where the statistics log entry persists in the persistent memory region until the statistics log entry is read back through the memory controller.

Abstract: An access device may be implemented to provide one or more access channels to non-volatile memory. Memory mapping implemented at the access device may direct a memory controller of the access device to perform access requests, replacing an initial storage location with a different storage location to access in the non-volatile memory device. Address scrambling, encryption, and other modifications to performing an access request may be implemented at the access device, in some embodiments, in addition to the memory mapping techniques.

Abstract: Provided are systems and methods for packet policing for controlling the rate of packet flows. In some implementations, an integrated circuit is provided. The integrated circuit may comprise a memory, a counter, and a pipeline. The integrated circuit may be operable to, upon receiving packet information describing a packet, determine, using the pipeline, a drop status for the packet. Determining the drop status may include determining a previous number of credits available, a number of new credits available, a current number of credits available, and a number of credits needed to transmit the packet. The drop status may be determined by comparing the number of credits needed to transmit the packet against the current number of credits available. The integrated circuit may further update the information stored for a policing context in the memory based on the drop status and the number of credits needed to transmit the packet.

Abstract: Disclosed herein are methods and apparatuses related to the use of counter tables. A counter table can comprise a plurality of lower-level counters and an upper-level counter. A range of values capable of being represented by a lower-level counter from the plurality of lower-level counters can be enlarged by associating the lower-level counter with the upper-level counter. A counter table can be associated with a network device.

Abstract: A circuit at an interface between a device and an interconnect fabric is configured to track outstanding transactions associated with the device and ensure the completion of the outstanding transactions before rebooting or powering down the device. In some embodiments, the circuit is also configurable to provide appropriate responses when the device is powered down or is being rebooted such that other devices in the system can still operate even without knowing that the device is inactive and would not hang because no response is received from the device.

Abstract: A microcontroller may be implanted to manage migration events performed by a separate memory controller to non-volatile memory. Migration events, such as failed writes at the memory controller or wear leveling migrations to move data from one storage location to another may be detected by the microcontroller. The destination location and the data to be migrated may be identified by the microcontroller. The microcontroller may then instruct the memory controller to copy the data to the destination location.

Abstract: Provided are systems and methods for modifying a forwarding decision for a packet being processed by a network device. The forwarding decision can include a final determination whether to forward the packet from the network device and onto a network. In various implementations, an integrated circuit device of the network device can receive packet information for the packet, where the packet information includes a forwarding decision. The forwarding decision can include a decision type. The integrated circuit device can further determine a redirection includes using the decision type. The redirection information can include a redirection entry for each of one or more decision types. The integrated circuit device can further modify the packet information using values from the particular redirection entry, excluding modification of values associated with an outbound packet header that can be used to forward the particular packet.

Abstract: Disclosed herein are techniques for monitoring the performance of a storage-class memory (SCM). In some embodiments, a performance monitoring circuit at an interface between the SCM and a memory controller of the SCM receives transaction commands from the memory controller to the SCM, measures statistics associated with the transaction commands, and determines a utilization rate of the SCM based on the statistics. Based on the determined utilization rate of the SCM, future transaction requests can be optimized to improve the utilization rate of the SCM.

Abstract: Disclosed are techniques that can be used to efficiently collect statistical or other information from many registers in an integrated circuit without substantially burdening a central processing unit. The techniques can use logic that, without being directed by a central processing unit, can periodically collect information from a plurality of disparate registers of an integrated circuit and move the contents of the registers to memory (e.g., volatile memory accessible by the central processing unit) other than the registers.

Abstract: Failed write handling can be implemented at a memory controller for non-volatile memory. Failure of a write to a storage location in the non-volatile memory may be detected. An indication of the failure may be sent to a microcontroller for the non-volatile memory which may return an instruction to write to a different location in the non-volatile memory. Reads and writes to the storage location of the failed write may still be allowed, in some embodiments, by redirecting the reads and writes to a copy of data of the failed write stored in a copy buffer in the memory controller.

Abstract: Provided are systems and methods for packet policing for controlling the rate of a packet flows. In some implementations, an integrated circuit is provided. The integrated circuit may comprise a memory, a counter, and a pipeline. The integrated circuit may be operable to, upon receiving packet information describing a packet, determine, using the pipeline, a drop status for the packet. Determining the drop status may include determining a previous number of credits available, a number of new credits available, a current number of credits available, and a number of credits needed to transmit the packet. The drop status may be determined by comparing the number of credits needed to transmit the packet against the current number of credits available. The integrated circuit may further update the information stored for a policing context in the memory based on the drop status and the number of credits needed to transmit the packet.

Abstract: Disclosed herein are methods and apparatuses related to the use of counter tables. A counter table can comprise a plurality of lower-level counters and an upper-level counter. A range of values capable of being represented by a lower-level counter from the plurality of lower-level counters can be enlarged by associating the lower-level counter with the upper-level counter. A counter table can be associated with a network device.

Abstract: Provided are systems and methods for packet policing for controlling the rate of packet flows. In some implementations, an integrated circuit is provided. The integrated circuit may comprise a memory, a counter, and a pipeline. In some implementations, the integrated circuit may receive first packet information that describes a first packet, and subsequently receive second packet information that describes a second packet. The integrated circuit may process the first packet information concurrently with processing the second packet information. Processing each of the packet information may include determining, using the pipeline, a drop status for each packet, wherein determining the drop status includes determining, using the counter, the packet information, and a policing context, whether sufficient credits are available to transmit each packet. The integrate circuit may then provide the drop status for the second packet subsequent to providing the drop status for the first packet.

Abstract: A programmable switch fabric can allow dynamic path selection for a specific class of packets using programmable action codes. Multiple packet processors inside a switch can process an incoming packet simultaneously and can make a decision (e.g., drop, forward, copy, etc.) related to the packet. A specific reassignment action code can be associated with the decision that needs to be prevailed for a specific class of packets. A priority arbiter can reassign the priority based on the specific reassignment action code so that the action associated with that action code prevails in the decision provided by the priority arbiter.