Patents by Inventor Mark B. Lesser

Mark B. Lesser has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multi-phase and gate
    Patent number: 4100430
    Abstract: A no-delay, ratioless AND gate compatible with a four-phase, major-minor clocking scheme and a six-phase metal oxide semiconductor (MOS) system. The disclosed AND gate can be implemented by the interconnection of first and second field effect transistors having conduction paths thereof selectively connected between a respective input terminal and the output terminal of the AND gate to precharge and conditionally discharge the output terminal.
    Type: Grant
    Filed: March 7, 1977
    Date of Patent: July 11, 1978
    Assignee: Rockwell International Corporation
    Inventor: Mark B. Lesser
  • Dynamic logic gate
    Patent number: 4044270
    Abstract: An improved dynamic logic gate compatible with a four-phase, major-minor clocking scheme and a six-phase metal oxide semiconductor (MOS) system. The gate evaluates only during an in-between clock phase, which phase corresponds to the interval of time between the occurrence of first and second major clock phases.
    Type: Grant
    Filed: June 21, 1976
    Date of Patent: August 23, 1977
    Assignee: Rockwell International Corporation
    Inventor: Mark B. Lesser
  • In-between phase clamping circuit to reduce the effects of positive noise
    Patent number: 4042833
    Abstract: An improved MOS clamping circuit compatible with a multi-phase, major-minor clocking scheme. The present circuit is adapted to clamp the output terminal of a conventional major logic gate to a negative signal level. The instant clamping circuit prevents the deterioration of the logic gate output signal as a consequence of positive noise during the minor clock phases and during an in-between clock phase, which phase corresponds to the interval of time between the occurrence of first and second major clock phases.
    Type: Grant
    Filed: August 25, 1976
    Date of Patent: August 16, 1977
    Assignee: Rockwell International Corporation
    Inventor: Mark B. Lesser