Patents by Inventor Mark B. Ritter

Mark B. Ritter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10671911
    Abstract: Embodiments are directed to a driver circuit including a first amplifier having a voltage follower configured to control a first node to maintain a voltage of the first node at a constant value. By maintaining the first node voltage, the first amplifier having the voltage follower is further configured to have a first amplifier output current into the first node at a value without the effect of the voltage fluctuation. The driver circuit further includes a second amplifier configured to control a second node, wherein the second amplifier is in a current mirror configuration with respect to the first amplifier such that a second amplifier current output is a highly precise mirror of the first amplifier current output.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: June 2, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark B. Ritter, Takeo Yasuda
  • Patent number: 10643125
    Abstract: Embodiments include methods and systems of neuron leaky integrate and fire circuit (NLIFC). Aspects include: receiving an input current having both AC component and DC component at an input terminal of the NLIFC, extracting AC component of input current, generating a number of swing voltages at a swing node using extracted AC component of the input current, transferring charge from a pull-up node to a neuron membrane potential (NP) node through an integration diode and a pull-up diode to raise a voltage at NP node over an integration capacitor gradually and the voltage at NP node shows integration value of AC component of input current, implementing leaky decay function of the neuron leaky integrate and fire circuit, detecting a timing of neuron fire using an analog comparator, resetting a neuron membrane potential level for a refractory period after neuron fire, and generating fire output signal of the NLIFC.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: May 5, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark B. Ritter, Takeo Yasuda
  • Publication number: 20200026994
    Abstract: Embodiments include methods and systems of neuron leaky integrate and fire circuit (NLIFC). Aspects include: receiving an input current having both AC component and DC component at an input terminal of the NLIFC, extracting AC component of input current, generating a number of swing voltages at a swing node using extracted AC component of the input current, transferring charge from a pull-up node to a neuron membrane potential (NP) node through an integration diode and a pull-up diode to raise a voltage at NP node over an integration capacitor gradually and the voltage at NP node shows integration value of AC component of input current, implementing leaky decay function of the neuron leaky integrate and fire circuit, detecting a timing of neuron fire using an analog comparator, resetting a neuron membrane potential level for a refractory period after neuron fire, and generating fire output signal of the NLIFC.
    Type: Application
    Filed: September 26, 2019
    Publication date: January 23, 2020
    Inventors: Mark B. Ritter, Takeo Yasuda
  • Patent number: 9793913
    Abstract: A probabilistic digitizer for extracting information from a Josephson comparator is disclosed. The digitizer uses statistical methods to aggregate over a set of comparator readouts, effectively increasing the sensitivity of the comparator even when an input signal falls within the comparator's gray zone. Among other uses, such a digitizer may be used to discriminate between states of a qubit.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: October 17, 2017
    Assignee: International Business Machines Corporation
    Inventors: John F. Bulzacchelli, Mark B. Ketchen, Christopher B. Lirakis, Alexey Y. Lvov, Stanislav Polonsky, Mark B. Ritter
  • Publication number: 20170255860
    Abstract: Embodiments include methods and systems of neuron leaky integrate and fire circuit (NLIFC). Aspects include: receiving an input current having both AC component and DC component at an input terminal of the NLIFC, extracting AC component of input current, generating a number of swing voltages at a swing node using extracted AC component of the input current, transferring charge from a pull-up node to a neuron membrane potential (NP) node through an integration diode and a pull-up diode to raise a voltage at NP node over an integration capacitor gradually and the voltage at NP node shows integration value of AC component of input current, implementing leaky decay function of the neuron leaky integrate and fire circuit, detecting a timing of neuron fire using an analog comparator, resetting a neuron membrane potential level for a refractory period after neuron fire, and generating fire output signal of the NLIFC.
    Type: Application
    Filed: March 3, 2016
    Publication date: September 7, 2017
    Inventors: Mark B. Ritter, Takeo Yasuda
  • Publication number: 20170243108
    Abstract: Embodiments are directed to a driver circuit including a first amplifier having a voltage follower configured to control a first node to maintain a voltage of the first node at a constant value. By maintaining the first node voltage, the first amplifier having the voltage follower is further configured to have a first amplifier output current into the first node at a value without the effect of the voltage fluctuation. The driver circuit further includes a second amplifier configured to control a second node, wherein the second amplifier is in a current mirror configuration with respect to the first amplifier such that a second amplifier current output is a highly precise mirror of the first amplifier current output.
    Type: Application
    Filed: February 19, 2016
    Publication date: August 24, 2017
    Inventors: Mark B. Ritter, Takeo Yasuda
  • Publication number: 20170179973
    Abstract: A probabilistic digitizer for extracting information from a Josephson comparator is disclosed. The digitizer uses statistical methods to aggregate over a set of comparator readouts, effectively increasing the sensitivity of the comparator even when an input signal falls within the comparator's gray zone. Among other uses, such a digitizer may be used to discriminate between states of a qubit.
    Type: Application
    Filed: February 20, 2017
    Publication date: June 22, 2017
    Inventors: John F. Bulzacchelli, Mark B. Ketchen, Christopher B. Lirakis, Alexey Y. Lvov, Stanislav Polonsky, Mark B. Ritter
  • Patent number: 9614532
    Abstract: A probabilistic digitizer for extracting information from a Josephson comparator is disclosed. The digitizer uses statistical methods to aggregate over a set of comparator readouts, effectively increasing the sensitivity of the comparator even when an input signal falls within the comparator's gray zone. Among other uses, such a digitizer may be used to discriminate between states of a qubit.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: April 4, 2017
    Assignee: International Business Machines Corporation
    Inventors: John F. Bulzacchelli, Mark B. Ketchen, Christopher B. Lirakis, Alexey Y. Lvov, Stanislav Polonsky, Mark B. Ritter
  • Publication number: 20170047914
    Abstract: A pulse generator and a method of fabricating a pulse generator are described. The pulse generator includes an input node to receive an input voltage, a first capacitor, and a second capacitor. The first capacitor is positioned between the input node and the second capacitor. An output node outputs an output voltage with a pulse shape, and the pulse generator also includes at least one switch between the input node and the second capacitor. The at least one switch controls the pulse shape of the output voltage.
    Type: Application
    Filed: August 12, 2015
    Publication date: February 16, 2017
    Inventors: Kohji Hosokawa, Masatoshi Ishii, Mark B. Ritter, Takeo Yasuda
  • Publication number: 20170047911
    Abstract: A pulse generator and a method of fabricating a pulse generator are described. The pulse generator includes an input node to receive an input voltage, a first capacitor, and a second capacitor. The first capacitor is positioned between the input node and the second capacitor. An output node outputs an output voltage with a pulse shape, and the pulse generator also includes at least one switch between the input node and the second capacitor. The at least one switch controls the pulse shape of the output voltage.
    Type: Application
    Filed: November 23, 2015
    Publication date: February 16, 2017
    Inventors: Kohji Hosokawa, Masatoshi Ishii, Mark B. Ritter, Takeo Yasuda
  • Patent number: 9203022
    Abstract: A resistive switching device includes a first electrode and a transition metal oxide layer formed on the first electrode. An oxygen scavenging electrode is formed on the transition metal oxide wherein the oxygen scavenging electrode removes oxygen from the transition metal oxide layer to increase formation of oxygen vacancies in the transition metal oxide layer to enable a switching mode when a bias is applied between the first electrode and the oxygen scavenging electrode.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: December 1, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Marinus J. Hopstaken, Jeehwan Kim, Seyoung Kim, Mark B. Ritter
  • Publication number: 20150243888
    Abstract: A resistive switching device includes a first electrode and a transition metal oxide layer formed on the first electrode. An oxygen scavenging electrode is formed on the transition metal oxide wherein the oxygen scavenging electrode removes oxygen from the transition metal oxide layer to increase formation of oxygen vacancies in the transition metal oxide layer to enable a switching mode when a bias is applied between the first electrode and the oxygen scavenging electrode.
    Type: Application
    Filed: May 12, 2015
    Publication date: August 27, 2015
    Inventors: Marinus J. Hopstaken, Jeehwan Kim, Seyoung Kim, Mark B. Ritter
  • Patent number: 8949685
    Abstract: Techniques are disclosed for minimizing the effects of soft errors associated with memory devices that are individually accessible. By way of example, a method of organizing a column in a memory array of a memory device protected by an error correction code comprises the step of maximizing a distance of the error correction code by maximizing a physical distance between memory bits associated with a memory line within the column protected by the error correction code. Other soft error protection techniques may include use of a feed forward error correction code or use of a memory operation (e.g., read or write operation) suppress and retry approach.
    Type: Grant
    Filed: January 27, 2010
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Douglas J. Joseph, Mark B. Ritter, José A. Tierno
  • Publication number: 20150028279
    Abstract: A resistive switching device includes a first electrode and a transition metal oxide layer formed on the first electrode. An oxygen scavenging electrode is formed on the transition metal oxide wherein the oxygen scavenging electrode removes oxygen from the transition metal oxide layer to increase formation of oxygen vacancies in the transition metal oxide layer to enable a switching mode when a bias is applied between the first electrode and the oxygen scavenging electrode.
    Type: Application
    Filed: July 23, 2013
    Publication date: January 29, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marinus J. Hopstaken, Jeehwan Kim, Seyoung Kim, Mark B. Ritter
  • Patent number: 8832010
    Abstract: According to a technique, an electronic device is configured to correspond to characteristic features of a biological synapse. The electronic device includes multiple bipolar resistors arranged in parallel to form an electronic synapse, an axonal connection connected to one end of the electronic synapse and to a first electronic neuron, and a dendritic connection connected to another end of the electronic synapse and to a second electronic neuron. An increase and decrease of synaptic conduction in the electronic synapse is based on a probability of switching the plurality of bipolar resistors between a low resistance state and a high resistance state.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: September 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Bipin Rajendran, Mark B. Ritter
  • Patent number: 8832011
    Abstract: According to a technique, an electronic device is configured to correspond to characteristic features of a biological synapse. The electronic device includes multiple bipolar resistors arranged in parallel to form an electronic synapse, an axonal connection connected to one end of the electronic synapse and to a first electronic neuron, and a dendritic connection connected to another end of the electronic synapse and to a second electronic neuron. An increase and decrease of synaptic conduction in the electronic synapse is based on a probability of switching the plurality of bipolar resistors between a low resistance state and a high resistance state.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: September 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Bipin Rajendran, Mark B. Ritter
  • Publication number: 20130173516
    Abstract: According to a technique, an electronic device is configured to correspond to characteristic features of a biological synapse. The electronic device includes multiple bipolar resistors arranged in parallel to form an electronic synapse, an axonal connection connected to one end of the electronic synapse and to a first electronic neuron, and a dendritic connection connected to another end of the electronic synapse and to a second electronic neuron. An increase and decrease of synaptic conduction in the electronic synapse is based on a probability of switching the plurality of bipolar resistors between a low resistance state and a high resistance state.
    Type: Application
    Filed: January 4, 2012
    Publication date: July 4, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bipin Rajendran, Mark B. Ritter
  • Publication number: 20130173515
    Abstract: According to a technique, an electronic device is configured to correspond to characteristic features of a biological synapse. The electronic device includes multiple bipolar resistors arranged in parallel to form an electronic synapse, an axonal connection connected to one end of the electronic synapse and to a first electronic neuron, and a dendritic connection connected to another end of the electronic synapse and to a second electronic neuron. An increase and decrease of synaptic conduction in the electronic synapse is based on a probability of switching the plurality of bipolar resistors between a low resistance state and a high resistance state.
    Type: Application
    Filed: September 12, 2012
    Publication date: July 4, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bipin Rajendran, Mark B. Ritter
  • Patent number: 8429107
    Abstract: A system, method, and design structure for address-event-representation network simulation are provided. The system includes a hardware structure with a plurality of interconnected processing modules configured to simulate a plurality of interconnected nodes. To simulate each node, the hardware structure includes a source table configured to receive an input message and identify a weight associated with a source of the input message. The hardware structure also includes state management logic configured to update a node state as a function of the identified weight, and generate an output signal responsive to the updated node state. The hardware structure further includes a target table configured to generate an output message in response to the output signal, identify a target to receive the output message, and transmit the output message. The hardware structure may further include learning logic configured to combine information about input messages and generated output signals, and to update weights.
    Type: Grant
    Filed: November 4, 2009
    Date of Patent: April 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Monty M. Denneau, Daniel J. Friedman, Ralph Linsker, Mark B. Ritter
  • Patent number: 8161314
    Abstract: A method of and system for frequency clocking in a processor core are disclosed. In this system, at least one processor core is provided, and that at least one processor core has a clocking subsystem for generating an analog output clock signal at a variable frequency. Digital frequency control data and an analog signal are both transmitted to that at least one processor core; and that processor core uses the received analog signal and digital frequency control data to set the frequency of the output clock signal of the clocking subsystem. In a preferred implementation, multiple cores are asynchronously clocked and the core frequencies are independently set.
    Type: Grant
    Filed: April 12, 2007
    Date of Patent: April 17, 2012
    Assignee: International Business Machines Corporation
    Inventors: Lawrence Jacobowitz, Mark B. Ritter, Daniel J. Stigliani, Jr.