Abstract: An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test.

Abstract: In some embodiments an Integrated Circuit package includes a plurality of system functional pins, at least one system functional pin depopulation zone, and at least one non-system functional pin located in the at least one functional pin depopulation zone. Other embodiments are described and claimed.

Abstract: In some embodiments an Integrated Circuit package includes a plurality of system functional pins, at least one system functional pin depopulation zone, and at least one non-system functional pin located in the at least one functional pin depopulation zone. Other embodiments are described and claimed.

Abstract: In some embodiments an Integrated Circuit package includes a plurality of system functional pins, at least one system functional pin depopulation zone, and at least one non-system functional pin located in the at least one functional pin depopulation zone. Other embodiments are described and claimed.

Abstract: An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and de-bug of a part/platform under test.

Abstract: In some embodiments an Integrated Circuit package includes a plurality of system functional pins, at least one system functional pin depopulation zone, and at least one non-system functional pin located in the at least one functional pin depopulation zone. Other embodiments are described and claimed.

Abstract: In some embodiments an Integrated Circuit package includes a plurality of system functional pins, at least one system functional pin depopulation zone, and at least one non-system functional pin located in the at least one functional pin depopulation zone. Other embodiments are described and claimed.

Abstract: In some embodiments an Integrated Circuit package includes a plurality of system functional pins, at least one system functional pin depopulation zone, and at least one non-system functional pin located in the at least one functional pin depopulation zone. Other embodiments are described and claimed.

Abstract: In some embodiments an Integrated Circuit package includes a plurality of system functional pins, at least one system functional pin depopulation zone, and at least one non-system functional pin located in the at least one functional pin depopulation zone. Other embodiments are described and claimed.

Abstract: In some embodiments an Integrated Circuit package includes a plurality of system functional pins, at least one system functional pin depopulation zone, and at least one non-system functional pin located in the at least one functional pin depopulation zone. Other embodiments are described and claimed.

Abstract: A coupler is passively aligned over a substrate, wherein the coupler is laterally aligned to an optoelectronic (OE) device coupled to the substrate. The coupler is placed on the substrate, wherein the coupler is vertically aligned to the OE device. The coupler is fixed to the substrate.

Abstract: An assembly including a processor socket having a cut region. The assemble further including a probe board having a repeater positioned in alignment with the cut region. The repeater is to receive at least a first signal. The repeater is to tap the first signal. The tapped first signal is to be transmitted to a first device. The repeater is also to reinject the first signal, and the reinjected first signal to be transmitted to a processor.

Abstract: Circuit board and system with multi-portion sockets, and signal methods practiced thereon are described herein.

Abstract: A multi-portion socket, related components, and systems having such socket/components are described herein.

Abstract: A method for producing a heat sink includes extruding a first material in a second material, and cut into a billet. The second material is removed from the billet to produce a base and a plurality of fins. The second material is removed from the billet by placing the billet into a chemical bath. The heat sink is rinsed to remove chemical residue from the heat sink. Mounting holes are stamped into the base, and a mounting surface is ground on the heat sink. Another method for producing a heat sink includes ramming fins into a base. The base is heated prior to the entry of the fins. The base is also provided with dimples to accept entry of the fins.

Abstract: A method for producing a heat sink includes extruding a first material in a second material, and cut into a billet. The second material is removed from the billet to produce a base and a plurality of fins. The second material is removed from the billet by placing the billet into a chemical bath. The heat sink is rinsed to remove chemical residue from the heat sink. Mounting holes are stamped into the base, and a mounting surface is ground on the heat sink. Another method for producing a heat sink includes ramming fins into a base. The base is heated prior to the entry of the fins. The base is also provided with dimples to accept entry of the fins.

Abstract: A method for producing a heat sink includes extruding a first material in a second material, and cut into a billet. The second material is removed from the billet to produce a base and a plurality of fins. The second material is removed from the billet by placing the billet into a chemical bath. The heat sink is rinsed to remove chemical residue from the heat sink. Mounting holes are stamped into the base, and a mounting surface is ground on the heat sink. Another method for producing a heat sink includes ramming fins into a base. The base is heated prior to the entry of the fins. The base is also provided with dimples to accept entry of the fins.

Abstract: A socket includes a mechanism to gain electrical access to integrated circuit package pins in an end-user system. A pin grid array (PGA) socket includes signal traces that lead to a connector accessible by test equipment. In one embodiment, the PGA socket is a zero insertion force (ZIF) socket, and in other embodiments, the PGA socket is a low insertion force (LIF) socket. In other embodiments, multiple PGA sockets are interconnected.

Abstract: A method for producing a heat sink includes extruding a first material in a second material, and cut into a billet. The second material is removed from the billet to produce a base and a plurality of fins. The second material is removed from the billet by placing the billet into a chemical bath. The heat sink is rinsed to remove chemical residue from the heat sink. Mounting holes are stamped into the base, and a mounting surface is ground on the heat sink. Another method for producing a heat sink includes ramming fins into a base. The base is heated prior to the entry of the fins. The base is also provided with dimples to accept entry of the fins.

Abstract: An apparatus for electrically connecting electrical contact pads on a first circuit board to electrical contact pads on a second circuit board is disclosed. Conductive bumps coupled to signal wires on a support element mate with the electrical contact pads on the first and second circuit boards. The mating provides an electrical connection allowing signals to be transmitted between the circuit boards. Alignment holes and alignment circuitry provide a means for verifying that the proper conductive bumps are mating with the proper electrical contact pads.