Abstract: An electrostatic discharge (ESD) logging system includes ESD detection circuitry having at least one input electrically connected coupled to a node of an ESD protection circuit. The ESD detection circuitry provides a detector signal in response to detecting an ESD event at the node of the ESD protection circuit. Capture circuitry is electrically connected to an output of the ESD event detector. The capture circuitry asserts a capture signal to indicate the occurrence of the ESD event in response to the detector signal. A logic circuit provides a logic output in response to the capture signal.

Abstract: An electrostatic discharge (ESD) logging system includes ESD detection circuitry having at least one input electrically connected coupled to a node of an ESD protection circuit. The ESD detection circuitry provides a detector signal in response to detecting an ESD event at the node of the ESD protection circuit. Capture circuitry is electrically connected to an output of the ESD event detector. The capture circuitry asserts a capture signal to indicate the occurrence of the ESD event in response to the detector signal. A logic circuit provides a logic output in response to the capture signal.

Abstract: An electrostatic discharge (ESD) logging system includes ESD detection circuitry having at least one input electrically connected coupled to a node of an ESD protection circuit. The ESD detection circuitry provides a detector signal in response to detecting an ESD event at the node of the ESD protection circuit. Capture circuitry is electrically connected to an output of the ESD detection circuitry. The capture circuitry asserts a capture signal to indicate the occurrence of the ESD event in response to the detector signal. A logic circuit provides a logic output in response to the capture signal.

Abstract: An electrostatic discharge (ESD) logging system includes ESD detection circuitry having at least one input electrically connected coupled to a node of an ESD protection circuit. The ESD detection circuitry provides a detector signal in response to detecting an ESD event at the node of the ESD protection circuit. Capture circuitry is electrically connected to an output of the ESD detection circuitry. The capture circuitry asserts a capture signal to indicate the occurrence of the ESD event in response to the detector signal. A logic circuit provides a logic output in response to the capture signal.

Abstract: The accelerator output stage circuit includes: a high side output device coupled to an output node; a low side output device coupled to the output node; a first logic gate coupled to a control node of the first high side output device; a second logic gate coupled to a control node of the second high side output device; a high side one-shot device having an output coupled to a first input of the first logic gate; a low side one-shot device having an output coupled to a first input of the second logic gate; and a feedback device coupled between the output node and a second input of the first logic gate, and between the output node and a second input of the second logic gate, and between the output node and the input to the high side resistor bypass device, and between the output node and the input to the low side one-shot resistor bypass device.

Abstract: A transition detect circuit includes: a first input port referenced to a first supply voltage node and a second input port referenced to a second supply voltage node. The circuit simultaneously monitors both ports for transitions, and once a transition occurs, directly generates the translated control signals at its output. Once a transition occurs at the inputs, the translated control signal is generated at the output within at most two gate delays. The circuit has very low quiescent current.

Abstract: A blocking circuit technique achieves very low Ioff and Ioz leakage in low power digital logic devices that incorporate Ioff and overvoltage tolerance. The blocking circuit employs a diode-connected P-channel device in parallel with a PN diode. The diode-connected P-channel device provides enough forward leakage in the subthreshold region to keep Ioz through the upper output driver to a very low level (0.2 uA typical). Further, both the diode-connected P-channel device and the PN diode together provide enough reverse blocking capability to keep Ioff to a very low level (0.2 uA typical).