Abstract: In general, this disclosure relates to techniques for switching between media broadcast streams having varying levels of quality. In one example method, a processing pipeline of a communication device processes a first broadcast stream representing a first version of media content. The processing pipeline includes quality checkpoints at which broadcast stream quality may be determined, and receives a second, different broadcast stream that is broadcasted at another data rate. The second broadcast stream represents a second version of the media content of different media quality. The processing pipeline measures a quality of the first broadcast stream and a quality of the second broadcast stream at one or more of the quality checkpoints, and switches the processing from the first broadcast stream to the second broadcast stream if the quality of the second broadcast stream exceeds a defined threshold at one or more of the quality checkpoints.

Abstract: A current mobile multimedia signal time slice is captured using a mobile MM receiver in response to a current mobile multimedia stream-identifying command input. The current mobile multimedia signal time slice contains at least one portion of a currently selected mobile multimedia stream. At least one anticipated mobile multimedia time slice is selectively captured. The at least one anticipated mobile multimedia time slice contains at least one portion of a corresponding anticipated mobile multimedia stream.

Abstract: A digital rights management system includes an authentication module and a decryption module. If desired, the modules can be implemented in separate integrated circuits. The authentication module retrieves authentication information for protected content and powers down after the authentication information is retrieved. The decryption module decrypts the protected content based on the authentication information while the authentication module is powered down.

Abstract: A current mobile multimedia signal time slice is captured using a mobile MM receiver in response to a current mobile multimedia stream-identifying command input. The current mobile multimedia signal time slice contains at least one portion of a currently selected mobile multimedia stream. At least one anticipated mobile multimedia time slice is selectively captured. The at least one anticipated mobile multimedia time slice contains at least one portion of a corresponding anticipated mobile multimedia stream.

Abstract: A demodulated multimedia signal is generated based on a captured handheld multimedia signal or a captured terrestrial multimedia signal where the handheld multimedia signal is formatted for reproduction on a handheld device and the terrestrial multimedia signal is formatted for reproduction on a computer system. The demodulated multimedia signal or a decoded multimedia signal (based on the demodulated multimedia signal) is transferred to a computer system for visual and/or audible reproduction on a computer system or for transmission to another computer system. The video information associated with the transferred signal is scaled by the computer system prior to display to match the display characteristics and capabilities of the computer system. The transferred signal may correspond to multiple channels of multimedia signals thereby enabling the display of multiple multimedia signals at the same time.

Abstract: A rapid silicon processing arrangement significantly decreases the time from initial design to market introduction. Consistent with one embodiment of the present invention, the rapid silicon processing arrangement uses a deconfigurable and extendible reference-chip development platform that includes a programmable device such as an electronically reconfigurable gate array and an off-platform bus for communicating with external devices. The reference-chip development platform can be deconfigured by deselecting communicative activity by one or more of functional block macros. The external devices can be used with the reference-chip development platform to test a hardware representation of the synthesized subset of the functional block macros in the programmable device within the reference-chip development platform as extended by the off-platform bus. The approach significantly decreases the development time, from initial design to market introduction.

Abstract: A rapid silicon processing arrangement significantly decreases the time from initial design to market introduction. Consistent with one embodiment of the present invention, the rapid silicon processing arrangement uses a deconfigurable and extendible reference-chip development platform that includes a programmable device such as an electronically reconfigurable gate array and an off-platform bus for communicating with external devices. The reference-chip development platform can be deconfigured by deselecting communicative activity by one or more of functional block macros. The external devices can be used with the reference-chip development platform to test a hardware representation of the synthesized subset of the functional block macros in the programmable device within the reference-chip development platform as extended by the off-platform bus. The approach significantly decreases the development time, from initial design to market introduction.

Abstract: A rapid silicon processing arrangement significantly decreases the time from initial design to market introduction. Consistent with one embodiment of the present invention, rapid silicon processing arrangement uses a deconfigurable and extendible reference-chip development platform that includes a programmable device such as an electronically reconfigurable gate array and an off-platform bus for communicating with external devices. The reference-chip development platform can be deconfigured by deselecting communicative activity by one or more of functional block macros. The external devices can be used with the reference-chip development platform to test a hardware representation of the synthesized of the functional block macros in the programmable device within the reference-chip development platform as extended by the off-platform bus. The approach significantly decreases the development time, from initial design to market introduction.