Abstract: The disclosure relates in particular to an apparatus for disinfecting at least one room, in particular for one or more persons, preferably a dwelling space or treatment room, for example a treatment room in a building, in particular a sickroom, a patient room and/or an operating theatre, by means of an atomiser. Specifically, the apparatus is characterised in that the atomiser includes a rotatable bell cup for atomising a disinfectant into the room. The disclosure relates to an associated method and furthermore to the use of a bell cup for atomising a disinfectant in a room for, in particular, one or more persons.

Abstract: Novel modular smart management devices in the form of drop safes include the modular components of a chassis, door and technology cabinet. The drop safes enable retailers to make cash deposits quickly and safely within or near their own facilities. Various technology, including RFID readers, RFID tags, and other equipment allow the drop safes to identify each deposited bag. Employees utilize specialized apps on their mobile devices to facilitate deposit creation and other tasks. Novel methodologies for accessing the drop safes for emptying employ single-use, time-expiration type authorization codes along with other security measures to minimize risk and to provide other benefits. Novel structures along with methodologies for replacing, on-site, modular components with auto-detection of functionality during initialization and re-initialization enables for efficient replacement and upgrading of components, including the upgrading of safes to provide additional functionality.

Abstract: A data transfer device that comprises: a chassis; a backplane; a slot arranged within the chassis and configured to hold a card; and a connector system integrated on the backplane and configured to electrically couple the card with the backplane; wherein the connector system includes a group of connectors arranged along a length of the slot such that a plurality of cards with card lengths less than the length of the slot may be electrically coupled to the backplane within a single slot.

Abstract: A chip layout for a high speed semiconductor device is disclosed. The chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. A serial interface is centrally located to reduce latency, power and propagation delays. Stacked die that contain one or more devices with the chip layout are characterized by having improved latency, bandwidth, power consumption, and propagation delays.

Abstract: A data transfer device that comprises: a chassis; a backplane; a slot arranged within the chassis and configured to hold a card; and a connector system integrated on the backplane and configured to electrically couple the card with the backplane; wherein the connector system includes a group of connectors arranged along a length of the slot such that a plurality of cards with card lengths less than the length of the slot may be electrically coupled to the backplane within a single slot.

Abstract: A chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. Tx terminals are grouped contiguously to each other, and are segregated as a group to a given edge of the package, Rx terminals are similarly grouped and segregated to a different edge of the package. Tx and Rx data channels are disposed in a respective single layer of the package, or both are disposed in a same single layer of the package. Rx ports and Tx ports are located at an approximate center of the package, with Tx and Rx ports disposed on respective opposite sides of an axis bisecting the package. Data signals received by, and transmitted from, the chip flow in a same direction, from a first edge of the package to the center of the package and from the center of the package to a second edge of the package, respectively.

Abstract: Content addressable memory (CAM) devices use both hard and soft priority techniques to allocate entries of different priority therein. The priorities of multiple CAM array blocks within the CAM device may be programmed before or as entries are loaded therein and may be reprogrammed during operation as the allocation of entries within the CAM device changes. The allocation of entries may change in response to additions or deletions of entries or as entries are reprioritized. The CAM devices include preferred priority resolution circuits that can resolve competing soft and hard priorities between multiple hit signals that are generated in response to a search operation. Such hit signals may be active to reflect the presence of at least one matching entry within a CAM array block. The resolution of which active hit signal has the highest overall priority among many can be used to facilitate the identification of the location (e.g.

Abstract: A method for processing addresses having variable prefix lengths, including (1) applying an input address to a plurality of CAM blocks; (2) assigning different sets of CAM blocks to store prefixes of different lengths; (3) generating a hit signal and an index signal with each of the CAM blocks in response to the input address; (4) programming a plurality of routing values; (5) routing the hit signals to a priority encoder in an order determined by the routing values; (6) generating an output hit signal with the priority encoder in response to the hit signals; (7) selecting one of the routing values as an index routing value in response to the output hit signal; and (8) routing one of the index signals as an output index value in response to the index routing value. Circuitry for implementing the method is also provided.

Abstract: Content addressable memory (CAM) devices include error detection and correction (EDC) control circuits therein. The EDC control circuit operates to correct soft errors in entries within a plurality of internal CAM array blocks with, at most, limited interruption to other operations performed by the CAM device. The EDC control circuit utilizes a multi-bit check word associated with each entry to detect a soft error and perform one-bit error correction on the entry. The EDC control circuit is configured to be active during a background mode of operation when the CAM array blocks are undergoing search operations in a foreground mode of operation. A CAM array block may also include a column of dual-function check bit cells that are configured to operate as a column of CAM cells when necessary to replace a defective column of CAM cells.

Abstract: A CAM device includes an array of multi-compare port CAM cells therein. The CAM cells are configured to support concurrent search operations between multiple distinct search words and entries within the rows of the CAM array. These concurrent search operations may be performed in-sync with respective clock signals that are asynchronous relative to each other.

Abstract: A translation circuit for translating addresses between computer networks and an associated method of performing address translation for a computer system are provided. The translation circuit includes a content addressable memory (CAM) device having a CAM array that is logically divided into a plurality of CAM segments. First and second sets of CAM segments are designated to perform comparison operations for addresses having first and second widths, respectively. An instruction provided to the CAM device specifies an address translation having either the first or second width. A comparison operation is performed in the first set of segments if the instruction specifies an address translation of the first width. A comparison operation is performed in the second set of segments if the instruction specifies an address translation of the second width. In one embodiment, each segment has the same size, and includes a plurality of sub-segments, each having the same width.

Abstract: Disclosed herein is a catcher's chest protector which includes, among other things, a harness with one strap holding the neck of the chest protector firmly against the neck of the player and a second strap to hold the chest portion of the protector against the chest. The harness is designed to be quickly adjustable and secure for a variety of body sizes and shapes so that the protector can rapidly be switched between different players while still fitting them all well. The catcher's chest protector may also forego any metal or leather components so as to be washable in a fabric care machine for simplified care.

Abstract: A ball glove for use in games such as baseball and softball wherein the webbing of the glove is suspended in the crotch of the glove through the use of at least one energy absorbing connector. The energy absorbing connector being capable of absorbing more energy from an impacting ball than a traditional rigid connector can absorb. The energy absorbing connector may absorb energy through a plurality of mechanisms whether mechanical, electrical, chemical or others. In particular, an energy absorbing connector which dissipates energy through resisted motion is discussed.

Abstract: A method for processing addresses having variable prefix lengths, including (1) applying an input address to a plurality of CAM blocks; (2) assigning different sets of CAM blocks to store prefixes of different lengths; (3) generating a hit signal and an index signal with each of the CAM blocks in response to the input address; (4) programming a plurality of routing values; (5) routing the hit signals to a priority encoder in an order determined by the routing values; (6) generating an output hit signal with the priority encoder in response to the hit signals; (7) selecting one of the routing values as an index routing value in response to the output hit signal; and (8) routing one of the index signals as an output index value in response to the index routing value. Circuitry for implementing the method is also provided.

Abstract: A memory device (201) having left (203) and right (204) ports for communicating with left (205) and right (206) electronic devices, includes memory banks (401-0˜401-7), semaphore logic (302), and port coupling circuitry (403, 404, 405-0˜405-7, 406-0˜406-7, 407-0˜407-7). The semaphore logic generates bank access grant signals (313, 314) on a first received basis in response to bank access requests from the left and right electronic devices, and the port coupling circuitry couples selected memory banks to the left and right ports in response to the bank access grant signals. Also included in the memory device are mail-box registers (2500-0L˜2500-3L, 2500-0R˜2500-3R), interrupt generating circuitry (2514-0L˜2514-3L, 2514-0R˜2514-3R, 2900, 3000, 307, 308), and interrupt status and cause registers (3101L˜3102L, 3101R˜3102R, 3301L˜3302L, 3301R˜3302R).

Abstract: A memory device (201) having left (203) and right (204) ports for communicating with left (205) and right (206) electronic devices, includes memory banks (401-0.about.401-7), semaphore logic (302), and port coupling circuitry (403, 404, 405-0.about.405-7, 406-0.about.406-7, 407-0.about.407-7). The semaphore logic generates bank access grant signals (313, 314) on a first received basis in response to bank access requests from the left and right electronic devices, and the port coupling circuitry couples selected memory banks to the left and right ports in response to the bank access grant signals. Also included in the memory device are mail-box registers (2500-0L.about.2500-3L, 2500-0R.about.2500-3R), interrupt generating circuitry (2514-0L.about.2514-3L, 2514-0R.about.2514-3R, 2900, 3000, 307, 308), and interrupt status and cause registers (3101L.about.3102L, 3101R.about.3102R, 3301L.about.3302L, 3301R.about.3302R).

Abstract: A memory device (201) having left (203) and right (204) ports for communicating with left (205) and right (206) electronic devices, includes memory banks (401-0.about.401-7), semaphore logic (302), and port coupling circuitry (403, 404, 405-0.about.405-7, 406-0.about.406-7, 407-0.about.407-7). The semaphore logic generates bank access grant signals (313, 314) on a first received basis in response to bank access requests from the left and right electronic devices, and the port coupling circuitry couples selected memory banks to the left and right ports in response to the bank access grant signals. Also included in the memory device are mail-box registers (2500-0L.about.2500-3L, 2500-0R.about.2500-3R), interrupt generating circuitry (2514-0L.about.2514-3L, 2514-0R.about.2514-3R, 2900, 3000, 307, 308), and interrupt status and cause registers (3101L.about.3102L, 3101R.about.3102R, 3301L.about.3302L, 3301R.about.3302R).