Patents by Inventor Mark Beaumont
Mark Beaumont has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8856493Abstract: A method of rotating data in a plurality of processing elements comprises a plurality of shifting operations and a plurality of storing operations, with the shifting and storing operations coordinated to enable a three shears operation to be performed on the data. The plurality of storing operations is responsive to the processing element's positions.Type: GrantFiled: February 14, 2012Date of Patent: October 7, 2014Assignee: Micron Technology, Inc.Inventor: Mark Beaumont
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Publication number: 20120144155Abstract: A method of rotating data in a plurality of processing elements comprises a plurality of shifting operations and a plurality of storing operations, with the shifting and storing operations coordinated to enable a three shears operation to be performed on the data. The plurality of storing operations is responsive to the processing element's positions.Type: ApplicationFiled: February 14, 2012Publication date: June 7, 2012Inventor: Mark Beaumont
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Patent number: 8135940Abstract: A method of rotating data in a plurality of processing elements comprises a plurality of shifting operations and a plurality of storing operations, with the shifting and storing operations coordinated to enable a three shears operation to be performed on the data. The plurality of storing operations is responsive to the processing element's positions.Type: GrantFiled: March 15, 2011Date of Patent: March 13, 2012Assignee: Micron Technologies, Inc.Inventor: Mark Beaumont
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Publication number: 20110167240Abstract: A method of rotating data in a plurality of processing elements comprises a plurality of shifting operations and a plurality of storing operations, with the shifting and storing operations coordinated to enable a three shears operation to be performed on the data. The plurality of storing operations is responsive to the processing element's positions.Type: ApplicationFiled: March 15, 2011Publication date: July 7, 2011Inventor: Mark Beaumont
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Publication number: 20110138124Abstract: A cache, including a cache memory, is configurable to operate in a cache mode and a trace mode. When the cache is operating in the cache mode, the cache memory stores a copy of a portion of data that is stored in another memory external to the cache, and a received data access request is processed by retrieving a copy of a portion of data identified in the received data access request from the cache memory (if the cache memory stores a copy of the portion of data), or by forwarding the data access request to a data access request processing means external to the cache (if the cache memory does not store a copy of the portion of data). When the cache is operating in the trace mode, data access requests received by the cache are monitored and information relating to a received data access request is captured and stored in the cache memory.Type: ApplicationFiled: September 24, 2010Publication date: June 9, 2011Applicant: STMicroelectronics (Research & Development) LimitedInventors: Mark Hill, John Mark Beaumont
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Patent number: 7930518Abstract: A method for generating a reflection of data in a plurality of processing elements comprises shifting the data along, for example, each row in the array until each processing element in the row has received all the data held by every other processing element in that row. Each processing element stores and outputs final data as a function of its position in the row. A similar reflection along a horizontal line can be achieved by shifting data along columns instead of rows. Also disclosed is a method for reflecting data in a matrix of processing elements about a vertical line comprising shifting data between processing elements arranged in rows. An initial count is set in each processing element according to the expression (2×Col_Index) MOD (array size). In one embodiment, a counter counts down from the initial count in each processing element as a function of the number of shifts that have peen performed. Output is selected as a function of the current count.Type: GrantFiled: January 28, 2010Date of Patent: April 19, 2011Assignee: Micron Technology, Inc.Inventor: Mark Beaumont
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Patent number: 7913062Abstract: A method of rotating data in a plurality of processing elements comprises a plurality of shifting operations and a plurality of storing operations, with the shifting and storing operations coordinated to enable a three shears operation to be performed on the data. The plurality of storing operations is responsive to the processing element's positions.Type: GrantFiled: October 20, 2003Date of Patent: March 22, 2011Assignee: Micron Technology, Inc.Inventor: Mark Beaumont
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Publication number: 20100131737Abstract: A method for generating a reflection of data in a plurality of processing elements comprises shifting the data along, for example, each row in the array until each processing element in the row has received all the data held by every other processing element in that row. Each processing element stores and outputs final data as a function of its position in the row. A similar reflection along a horizontal line can be achieved by shifting data along columns instead of rows. Also disclosed is a method for reflecting data in a matrix of processing elements about a vertical line comprising shifting data between processing elements arranged in rows. An initial count is set in each processing element according to the expression (2×Col_Index)MOD(array size). In one embodiment, a counter counts down from the initial count in each processing element as a function of the number of shifts that have peen performed. Output is selected as a function of the current count.Type: ApplicationFiled: January 28, 2010Publication date: May 27, 2010Applicant: Micron Technology, Inc.Inventor: Mark Beaumont
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Patent number: 7676648Abstract: A method for generating a reflection of data in a plurality of processing elements comprises shifting the data along, for example, each row in the array until each processing element in the row has received all the data held by every other processing element in that row. Each processing element stores and outputs final data as a function of its position in the row. A similar reflection along a horizontal line can be achieved by shifting data along columns instead of rows. Also disclosed is a method for reflecting data in a matrix of processing elements about a vertical line comprising shifting data between processing elements arranged in rows. An initial count is set in each processing element according to the expression (2×Col_Index) MOD (array size). In one embodiment, a counter counts down from the initial count in each processing element as a function of the number of shifts that have peen performed. Output is selected as a function of the current count.Type: GrantFiled: October 20, 2003Date of Patent: March 9, 2010Assignee: Micron Technology, Inc.Inventor: Mark Beaumont
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Patent number: 7596678Abstract: A transpose of data appearing in a plurality of processing elements comprises shifting the data along diagonals of the plurality of processing elements until the processing elements in the diagonal have received the data held by every other processing element in that diagonal. Shifting along diagonals can be accomplished by executing pairs of horizontal and vertical shifts in the x-y directions or pairs of shifts in perpendicular directions, e.g., x-z. Each processing element stores data as its final output data as a function of the processing element's position. In one embodiment, an initial count is either loaded into each processing element or calculated locally based on the processing element's location. The initial count may be given by one of the following expressions: (x+y+1)MOD(array size); (C+R+1)MOD(array size); (C+y+1); or MOD(array size); or (x+R+1)MOD(array size).Type: GrantFiled: October 20, 2003Date of Patent: September 29, 2009Assignee: Micron Technology, Inc.Inventor: Mark Beaumont
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Patent number: 7581080Abstract: The present invention is capable of placing or loading input data into a 2D or 3D array of processing elements interconnected in a variety of ways, and moving the data around by using a combination of shifts, e.g. north, south, east, west, which can be combined in any desired manner. The exact type and combination of shifts depends upon the particular data manipulation desired. As the sifting proceeds, each processing element is presented with a plurality of different array values. Each processing element can conditionally load any of the values it sees into the output result. The timing of the loading is achieved by monitoring a local counter. In a preferred embodiment, when the value in the local counter is non-positive, the current array value is selected as the final output for the output result. In general, each local counter is initialized to a different positive value and, at certain points in the shifting process, the counter is decremented.Type: GrantFiled: October 20, 2003Date of Patent: August 25, 2009Assignee: Micron Technology, Inc.Inventor: Mark Beaumont
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Patent number: 7574466Abstract: A method for finding an extrema for an n-dimensional array having a plurality of processing elements, the method includes determining within each processing element a first dimensional extrema for a first dimension, wherein the first dimensional extrema is related to the local extrema of the processing elements in the first dimension and wherein the first dimensional extrema has a most significant byte and a least significant byte, determining within each processing element a next dimensional extrema for a next dimension of the n-dimensional array, wherein the next dimensional extrema is related to the first dimensional extrema and wherein the next dimensional extrema has a most significant byte and a least significant byte; and repeating the determining within each processing element a next dimensional extrema for each of the n-dimensions, wherein each of the next dimensional extrema is related to a dimensional extrema from a previously selected dimension.Type: GrantFiled: October 20, 2003Date of Patent: August 11, 2009Assignee: Micron Technology, Inc.Inventor: Mark Beaumont
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Patent number: 7503046Abstract: A method of determining an interleave pattern for n lots of A and y lots of B, when n plus y equals a power of two such that the expression 2z?n may be used to represent the value of y, includes generating a key including the reverse bit order of a serially indexed count from 0 to 2z. An interleave pattern can be generated from the key in which all values less than n are replace by A and all other values are replaced by B. The key can be used to generate a table that contains all possible combinations of values of A and B. The table can then be stored such that an interleave pattern can be automatically selected based on either the number of lots of A or the number of lots of B.Type: GrantFiled: October 20, 2003Date of Patent: March 10, 2009Assignee: Micron Technology, Inc.Inventor: Mark Beaumont
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Patent number: 7472392Abstract: One aspect of the present invention relates to a method for balancing the load of an n-dimensional array of processing elements (PEs), wherein each dimension of the array includes the processing elements arranged in a plurality of lines and wherein each of the PEs has a local number of tasks associated therewith. The method comprises balancing at least one line of PEs in a first dimension, balancing at least one line of PEs in a next dimension, and repeating the balancing at least one line of PEs in a next dimension for each dimension of the n-dimensional array. The method may further comprise selecting one or more lines within said first dimension and shifting the number of tasks assigned to PEs in said selected one or more lines.Type: GrantFiled: October 20, 2003Date of Patent: December 30, 2008Assignee: Micron Technology, Inc.Inventor: Mark Beaumont
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Patent number: 7454451Abstract: A method for finding a local extrema for a single processing element having a set of values associated therewith includes separating the set of values into an odd set of values and an even set of values, determining a first extrema from the odd set of values, determining a second extrema from the even set of values, and determining the local extrema from the first extrema and the second extrema. The first extrema is found by comparing each odd-numbered value in the set to each other odd-numbered value in the set and the second extrema is found by comparing each even-numbered value in the set to each other even-numbered value in the set.Type: GrantFiled: October 20, 2003Date of Patent: November 18, 2008Assignee: Micron Technology, Inc.Inventor: Mark Beaumont
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Patent number: 7447720Abstract: A method for finding an extrema for an n-dimensional array having a plurality of processing elements, the method includes determining within each of the processing elements a dimensional extrema for a first dimension of the n-dimensional array, wherein the dimensional extrema is related to one or more local extrema of the processing elements in the first dimension, determining within each of the processing elements a next dimensional extrema for a next dimension of the n-dimensional array, wherein the next dimensional extrema is related to one or more of the first dimensional extrema, and repeating the determining within each of the processing elements a next dimensional extrema for each of the n-dimensions, wherein each of the next dimensional extrema is related to a dimensional extrema from a previously selected dimension.Type: GrantFiled: October 20, 2003Date of Patent: November 4, 2008Assignee: Micron Technology, Inc.Inventor: Mark Beaumont
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Patent number: 7448038Abstract: One aspect of the present invention relates to a method for balancing the load of a parallel processing system having a plurality of parallel processing elements arranged in a loop, wherein each processing element has a local number of tasks associated therewith. The method comprises determining within each processing element a total number of tasks present within the loop, calculating a local mean number of tasks within each processing element, assigning a weight to each of said plurality of processing elements, and calculating a local weighted deviation within each processing element. The method also comprises determining the sum weighted deviations within each processing element for one-half the loop in an anti-clockwise direction and in a clockwise direction, determining clockwise and anti-clockwise transfer parameters within each processing element, and redistributing tasks among the processing elements in response to the clockwise and anti-clockwise transfer parameters.Type: GrantFiled: October 20, 2003Date of Patent: November 4, 2008Assignee: Micron Technology, Inc.Inventor: Mark Beaumont
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Patent number: 7437726Abstract: A method for calculating a local mean number of tasks for each processing element (PEr) in a parallel processing system, wherein each processing element (PEr) has a local number of tasks associated therewith and wherein r represents the number for a selected processing element, the method comprising assigning a value (Er) to the each processing element (PEr), summing a total number of tasks present on the parallel processing system and the value (Er) for the each processing element (PEr), dividing the sum of the total number of tasks present on the parallel processing system and the value (Er) for the each processing element (PEr) by a total number of processing elements in the parallel processing system and truncating a fractional portion of the divided sum for the each processing element.Type: GrantFiled: October 20, 2003Date of Patent: October 14, 2008Assignee: Micron Technology, Inc.Inventor: Mark Beaumont
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Patent number: 7437729Abstract: A method for balancing the load of a parallel processing system having a plurality of parallel processing elements arranged in a loop, wherein each processing element has a local number of tasks associated therewith comprising determining within each processing element a total number of tasks present within the loop, calculating a local mean number of tasks within each processing element, and calculating a local deviation within each processing element. The method also comprises determining the sum deviations within each processing element for one-half the loop in an anti-clockwise direction and in a clockwise direction, determining clockwise and anti-clockwise transfer parameters within each processing element, and redistributing tasks among the processing elements in response to the clockwise and anti-clockwise transfer parameters.Type: GrantFiled: October 20, 2003Date of Patent: October 14, 2008Assignee: Micron Technology, Inc.Inventor: Mark Beaumont
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Patent number: 7430742Abstract: A method for balancing the load of a parallel processing system having parallel processing elements (PEs) linked serially in a line with first and second ends, wherein each of the PEs has a local number of tasks associated therewith, the method comprising determining a total number of tasks present on the line; notifying each of the PEs of the total number of tasks, calculating a local mean number of tasks for each of the PEs, and calculating a local deviation for each of the PEs. The method also comprises determining a first local cumulative deviation for each of the PEs, determining a second local cumulative deviation for each of the PEs, and redistributing tasks among the PEs in response to the first local cumulative deviation and the second local cumulative deviation.Type: GrantFiled: October 20, 2003Date of Patent: September 30, 2008Assignee: Micron Technology, Inc.Inventor: Mark Beaumont