Patents by Inventor Mark Beiley

Mark Beiley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7330993
    Abstract: According to one embodiment a computer system is disclosed. The computer system includes a bus and a chipset coupled to the bus. The chipset detects the slew rate of a signal transmitted over the bus by the chipset. In addition the chipset adjusts the slew rate based upon the state of the signal.
    Type: Grant
    Filed: September 29, 2003
    Date of Patent: February 12, 2008
    Assignee: Intel Corporation
    Inventors: Mahesh J. Deshmane, Mark A. Beiley, Luke A. Johnson
  • Patent number: 7061224
    Abstract: A method of testing a delay lock loop circuit is provided which comprises receiving an input signal and configuring the delay lock loop to generate a delay lock loop output signal based on the input signal. The method further comprises generating a test output signal from the input signal and delay lock loop output signal indicative of a relationship between a transition on the input signal and a transition on delay lock loop output signal.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: June 13, 2006
    Assignee: Intel Corporation
    Inventors: Akira Kakizawa, Mark Beiley, Mamun Ur Rashid
  • Patent number: 7024565
    Abstract: A circuit includes a capacitor formed with a dielectric including the dielectric encasing elements of the circuit. A detector detects changes in the capacitance of the capacitor.
    Type: Grant
    Filed: December 17, 1999
    Date of Patent: April 4, 2006
    Assignee: Intel Corporation
    Inventors: Mark A. Beiley, James E. Breisch
  • Publication number: 20060066291
    Abstract: A method of testing a delay lock loop circuit is provided which comprises receiving an input signal and configuring the delay lock loop to generate a delay lock loop output signal based on the input signal. The method further comprises generating a test output signal from the input signal and delay lock loop output signal indicative of a relationship between a transition on the input signal and a transition on delay lock loop output signal.
    Type: Application
    Filed: September 24, 2004
    Publication date: March 30, 2006
    Inventors: Akira Kakizawa, Mark Beiley, Mamun Rashid
  • Patent number: 6933168
    Abstract: A method and apparatus for employing a light shield to modulate pixel color responsivity. The improved pixel includes a substrate having a photodiode with a light receiving area. A color filter array material of a first color is disposed above the substrate. The pixel has a first relative responsivity. A light shield is disposed above the substrate to modulate the pixel color responsivity. The light shield forms an aperture whose area is substantially equal to the light receiving area adjusted by a reduction factor. The reduction factor is the result of an arithmetic operation between the first relative responsivity and a second relative responsivity, associated with a second pixel of a second color.
    Type: Grant
    Filed: March 9, 2001
    Date of Patent: August 23, 2005
    Assignee: Intel Corporation
    Inventors: Edward J. Bawolek, Lawrence T. Clark, Mark A. Beiley
  • Publication number: 20050071706
    Abstract: According to one embodiment a computer system is disclosed. The computer system includes a bus and a chipset coupled to the bus. The chipset detects the slew rate of a signal transmitted over the bus by the chipset. In addition the chipset adjusts the slew rate based upon the state of the signal.
    Type: Application
    Filed: September 29, 2003
    Publication date: March 31, 2005
    Inventors: Mahesh Deshmane, Mark Beiley, Luke Johnson
  • Patent number: 6806569
    Abstract: A mechanism is provided for delivering power to an on-die component (such as a buffer circuit). This may include a package unit having a low frequency delivery path and a high frequency delivery path and a die having the on-die component and a capacitive device each coupled in parallel between a first node and a second node. The die may further include a low frequency reception path and a high frequency reception path. The low frequency reception path may couple to the low frequency delivery path on the package unit and to the first node. The high frequency reception path may couple to the high frequency delivery path on the package unit and to the first node. The high frequency reception path may include a damping resistor.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: October 19, 2004
    Assignee: Intel Corporation
    Inventors: James E. Breisch, Mark A. Beiley
  • Publication number: 20040183171
    Abstract: A mechanism is provided for delivering power to an on-die component (such as a buffer circuit). This may include a package unit having a low frequency delivery path and a high frequency delivery path and a die having the on-die component and a capacitive device each coupled in parallel between a first node and a second node. The die may further include a low frequency reception path and a high frequency reception path. The low frequency reception path may couple to the low frequency delivery path on the package unit and to the first node. The high frequency reception path may couple to the high frequency delivery path on the package unit and to the first node. The high frequency reception path may include a damping resistor.
    Type: Application
    Filed: September 28, 2001
    Publication date: September 23, 2004
    Inventors: James E. Breisch, Mark A. Beiley
  • Publication number: 20040012029
    Abstract: A method and apparatus for employing a light shield to modulate pixel color responsivity. The improved pixel includes a substrate having a photodiode with a light receiving area. A color filter array material of a first color is disposed above the substrate. The pixel has a first relative responsivity. A light shield is disposed above the substrate to modulate the pixel color responsivity. The light shield forms an aperture whose area is substantially equal to the light receiving area adjusted by a reduction factor. The reduction factor is the result of an arithmetic operation between the first relative responsivity and a second relative responsivity, associated with a second pixel of a second color.
    Type: Application
    Filed: March 9, 2001
    Publication date: January 22, 2004
    Inventors: Edward J. Bawolek, Lawrence T. Clark, Mark A. Beiley
  • Patent number: 6522357
    Abstract: In a pixel having an electronic shutter, a method of increasing the retention time of the electronic shutter is disclosed. A reset signal is employed to drive a diode node to a predetermined voltage immediately after integration is completed. A sample signal is employed to control a pass gate. The sample signal includes a state where the sample signal is a negative voltage.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: February 18, 2003
    Assignee: Intel Corporation
    Inventors: Mark A. Beiley, Eric J. Hoffman, Lawrence T. Clark
  • Publication number: 20020156953
    Abstract: A dynamic bus inversion method transfers successive groups of bit signals across a data communications bus. The method determines the number (A) of bit signals in a current group of bit signals that will transition in state compared to the corresponding bit signals of a previous group of bit signals if the bit signals of the current group are inverted and the number (B) of bit signals in a current group of bit signals that will transition in state compared to the corresponding bit signals of a previous group of bit signals if the bit signals of the current group are not inverted. The bit signals of the current group are inverted before being transferred across the data communications bus if (A) is less than (B).
    Type: Application
    Filed: February 28, 2001
    Publication date: October 24, 2002
    Inventors: Mark A. Beiley, James Breisch
  • Patent number: 6438276
    Abstract: What is disclosed is an apparatus for reducing row reset noise in photodiode based complementary metal oxide (CMOS) sensors. The apparatus uses at least one reference pixel for each row of pixels in a sensor array. Also, a reset noise elimination unit is provided to adjust the values received from the pixels in a particular row by an adjustment value determined from the reset values received from the reference pixels. Additionally, a method of using the apparatus is disclosed. The method has a step of providing a first reset signal to a row of pixels including the reference pixels. The method also reads out a first set of values from this row after integration. The method continues with providing a second reset signal to the row and a second set of values is read from the row. An adjustment value is calculated from the difference of the values which are read out from the reference pixels.
    Type: Grant
    Filed: September 11, 2000
    Date of Patent: August 20, 2002
    Assignee: Intel Corporation
    Inventors: Jon M. Dhuse, Kevin M. Connolly, Mark A. Beiley
  • Patent number: 6433822
    Abstract: An architecture for self-calibration and fixed-pattern noise removal in imager chips. The column-to-column fixed pattern noise and/or pixel-to-pixel fixed pattern noise is determined through a self-calibration operation. During operation of the imager chip, when a value of a pixel is read, the read value is compensated with the fixed-pattern noise corresponding to either the column fixed pattern noise corresponding to the column having the pixel from which the value was read or to the pixel fixed pattern noise corresponding to the pixel from which the value was read.
    Type: Grant
    Filed: March 31, 1998
    Date of Patent: August 13, 2002
    Assignee: Intel Corporation
    Inventors: Lawrence T. Clark, Mark A. Beiley, Eric J. Hoffman
  • Publication number: 20020085106
    Abstract: In a pixel having an electronic shutter, a method of increasing the retention time of the electronic shutter is disclosed. A reset signal is employed to drive a diode node to a predetermined voltage immediately after integration is completed. A sample signal is employed to control a pass gate. The sample signal includes a state where the sample signal is a negative voltage.
    Type: Application
    Filed: September 30, 1997
    Publication date: July 4, 2002
    Inventors: MARK A. BEILEY, ERIC J. HOFFMAN, LAWRENCE T. CLARK
  • Patent number: 6410359
    Abstract: Leakage current may be reduced in trench isolated semiconductor devices by providing a buffer between the trench isolation and an active area. For example, with a trench isolated photodiode, a buffer of opposite conductivity type may be provided between the trench and the diffusion that forms the p-n junction of the photodiode.
    Type: Grant
    Filed: March 26, 2001
    Date of Patent: June 25, 2002
    Assignee: Intel Corporation
    Inventors: Kevin M. Connolly, Jung S. Kang, Berni W. Landau, James E. Breisch, Akira Kakizawa, Joseph W. Parks, Jr., Mark A. Beiley, Zong-Fu Li, Cory E. Weber, Shaofeng Yu
  • Patent number: 6366320
    Abstract: A semiconductor circuit having an analog storage array, a sense amplifier array in which each sense amp cell generates a differential signal pair in response to receiving first and second signals from the storage array. The circuit also includes an analog multiplexer through which a selected differential signal pair is driven into a signal processing pipe. In another embodiment, the sense amp cells each include an operational amplifier (opamp) pair configured as unity-gain closed loop amplifiers for driving the differential signal pair through the analog multiplexer. To improve settling time, the opamps are designed to provide an underdamped response while loaded with the analog transmission path through the analog mux. In yet another embodiment, each sense amp cell is activated one clock cycle before it is read. This allows speedy readout while transitioning from one cell to the next.
    Type: Grant
    Filed: December 8, 1997
    Date of Patent: April 2, 2002
    Assignee: Intel Corporation
    Inventors: Rajendran Nair, Mark A. Beiley, Morteza Afghahi
  • Patent number: 6362695
    Abstract: A circuit includes a first oscillator having transistors to produce a first signal with random variations resulting from device channel resistance of the transistors.
    Type: Grant
    Filed: December 21, 1999
    Date of Patent: March 26, 2002
    Assignee: Intel Corporation
    Inventors: Mark A. Beiley, James E. Breisch
  • Patent number: 6317154
    Abstract: A method for controlling a sensor to reduce reset noise is disclosed. The method including the steps of providing a reset command including a RESET signal and a first SAMPLE signal. The method also includes the steps of providing a read command including a first ADDRESS signal, a second SAMPLE signal, and a second ADDRESS signal. An apparatus including a system controller and a sensor controlled by the system controller is also disclosed. In one embodiment, the method and apparatus is provided for a sensor in a sensor array that is read-out in a pipelined fashion.
    Type: Grant
    Filed: March 2, 2001
    Date of Patent: November 13, 2001
    Assignee: Intel Corporation
    Inventor: Mark A. Beiley
  • Publication number: 20010019851
    Abstract: Leakage current may be reduced in trench isolated semiconductor devices by providing a buffer between the trench isolation and an active area. For example, with a trench isolated photodiode, a buffer of opposite conductivity type may be provided between the trench and the diffusion that forms the p-n junction of the photodiode.
    Type: Application
    Filed: March 26, 2001
    Publication date: September 6, 2001
    Inventors: Kevin M. Connolly, Jung S. Kang, Berni W. Landau, James E. Breisch, Akira Kakizawa, Joseph W. Parks, Mark A. Beiley, Zong-Fu Li, Cory E. Weber, Shaofeng Yu
  • Publication number: 20010007471
    Abstract: A method for controlling a sensor to reduce reset noise is disclosed. The method including the steps of providing a reset command including a RESET signal and a first SAMPLE signal. The method also includes the steps of providing a read command including a first ADDRESS signal, a second SAMPLE signal, and a second ADDRESS signal. An apparatus including a system controller and a sensor controlled by the system controller is also disclosed. In one embodiment, the method and apparatus is provided for a sensor in a sensor array that is read-out in a pipelined fashion.
    Type: Application
    Filed: March 2, 2001
    Publication date: July 12, 2001
    Inventor: Mark A. Beiley