Abstract: A method and apparatus for adaptively adjusting the operating voltage of an integrated circuit in response to tester-to-system variations, worst-case testing techniques, process variations, temperature variations, or reliability wearout mechanisms. The minimum operating voltage of an integrated circuit is determined either during external testing of the integrated circuit or during built-in-self-testing. The minimum operating voltage is transmitted to a variable voltage regulator where it is used to set the output of the regulator. The output of the regulator supplies the integrated circuit with its operating voltage. This technique enables tailoring of the operating voltage of integrated circuits on a part-by-part basis which results in power consumption optimization by adapting operating voltage in response to tester-to-system variations, worst-case testing techniques, process variations, temperature variations or reliability wearout mechanisms.

Abstract: A method and apparatus for adaptively adjusting the operating voltage of an integrated circuit in response to tester-to-system variations, worst-case testing techniques, process variations, temperature variations, or reliability wearout mechanisms. The minimum operating voltage of an integrated circuit is determined either during external testing of the integrated circuit or during built-in-self-testing. The minimum operating voltage is transmitted to a variable voltage regulator where it is used to set the output of the regulator. The output of the regulator supplies the integrated circuit with its operating voltage. This technique enables tailoring of the operating voltage of integrated circuits on a part-by-part basis which results in power consumption optimization by adapting operating voltage in response to tester-to-system variations, worst-case testing techniques, process variations, temperature variations or reliability wearout mechanisms.

Abstract: A method and apparatus for adaptively adjusting the operating voltage of an integrated circuit in response to tester-to-system variations, worst-case testing techniques, process variations, temperature variations, or reliability wearout mechanisms. The minimum operating voltage of an integrated circuit is determined either during external testing of the integrated circuit or during built-in-self-testing. The minimum operating voltage is transmitted to a variable voltage regulator where it is used to set the output of the regulator. The output of the regulator supplies the integrated circuit with its operating voltage. This technique enables tailoring of the operating voltage of integrated circuits on a part-by-part basis which results in power consumption optimization by adapting operating voltage in response to tester-to-system variations, worst-case testing techniques, process variations, temperature variations or reliability wearout mechanisms.

Abstract: An apparatus and method for dynamically allocating memory between inbound and outbound paths of a networking protocol handler so as to optimize the ratio of a given amount of memory between the inbound and outbound buffers is presented. Dedicated but sharable buffer memory is provided for both the inbound and outbound processors of a computer network. Buffer memory is managed so as to dynamically alter what portion of memory is used to receive and store incoming data packets or to transmit outgoing data packets. Use of the present invention reduces throttling of data rate transmissions and other memory access bottlenecks associated with conventional fixed-memory network systems.

Abstract: The invention provides micro-electromechanical switch (MEM) based designs for reducing the power consumption of logic blocks (e.g., latches) by isolating the logic blocks when they are non-operational. A power reduction circuit in accordance with the present invention comprises a logic block and at least one micro-electromechanical (MEM) switch for selectively disabling the logic block. MEM switches are provided for selectively: disconnecting the logic block from power; disconnecting the logic block from ground; providing a bypass line around the logic block; disconnecting an output of the logic block; and/or disconnecting an input of the logic block.

Abstract: Micro-electromechanical switches (MEMS) are configured to form a data storage latch to reduce power consumption, to reduce the space used in an integrated circuit, and to improve performance of the integrated circuit. MEMS are implemented at the wiring layer connected to an integrated circuit and coupled to form a storage latch.

Abstract: A method, system, and machine-readable medium having instructions recorded thereon are provided for valuing a current intellectual property (IP) transaction. The method includes providing IP data, financial data, and license data, the license data representing transactions other than the current IP transaction. A license value is obtained by referring to the license data. The value of the current IP transaction is determined by adjusting the license value in relation to the IP data, the financial data, and at least one of: i) trend data and ii) at least one quality factor.

Abstract: A method and apparatus for adaptively adjusting the operating voltage of an integrated circuit in response to tester-to-system variations, worst-case testing techniques, process variations, temperature variations, or reliability wearout mechanisms. The minimum operating voltage of an integrated circuit is determined either during external testing of the integrated circuit or during built-in-self-testing. The minimum operating voltage is transmitted to a variable voltage regulator where it is used to set the output of the regulator. The output of the regulator supplies the integrated circuit with its operating voltage. This technique enables tailoring of the operating voltage of integrated circuits on a part-by-part basis which results in power consumption optimization by adapting operating voltage in response to tester-to-system variations, worst-case testing techniques, process variations, temperature variations or reliability wearout mechanisms.