Abstract: An apparatus and method are disclosed for testing a hard macro that is embedded in a system on a chip (SOC) that is included in an integrated circuit chip. The SOC includes the hard macro. A logic design and operation of the hard macro are unknown. A test wrapper is embedded in the SOC. The test wrapper includes a scan chain. The test wrapper surrounds inputs and outputs of the hard macro. The test wrapper receives a known test data pattern in the scan chain that is included in the test wrapper. The hard macro receives from the test wrapper a set of non-test standard SOC inputs when the SOC is not in a test mode and receives the known test data pattern when the SOC is in the test mode. The hard macro generates a set of outputs in response to the inputs. The hard macro is tested utilizing the known test data pattern.

Abstract: A processor is disclosed including trace and profile logic for gathering and producing data corresponding to events occurring during instruction execution. In one embodiment, the trace and profile logic includes a serial queue for serializing data corresponding to a plurality of “discontinuity instructions” grouped together for simultaneous execution. A “discontinuity instruction” alters, or is executed as a result of an altering of, sequential instruction fetching.

Abstract: The present invention is an integrated circuit containing multiple digital signal processors (DSPs). A single host processor interface is also placed on the chip to connect the multiple DSPs to the host. A separate direct memory access (DMA) unit is provided for each DSP to facilitate flow of data to and from a data memory for each DSP. Each DSP also includes an instruction memory.

Abstract: A processor is disclosed including trace and profile logic for gathering and producing data corresponding to events occurring during instruction execution. In one embodiment, the trace and profile logic includes a discontinuity buffer for storing data corresponding to a “discontinuity instruction” subject to grouping with other instructions for simultaneous execution. A “discontinuity instruction” alters, or is executed as a result of an altering of, sequential instruction fetching. In another embodiment, the trace and profile logic includes a serial queue for serializing data corresponding to multiple discontinuity instructions grouped together for simultaneous execution. In another embodiment, the trace and profile logic includes stall filtering logic that asserts an output signal for a time period during which repeated data generated due to a pipeline stall condition are to be ignored.