Patents by Inventor Mark Bordelon

Mark Bordelon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230405665
    Abstract: A drawing unit with a segment reciprocating die for drawing metal segments comprises a tensioning device arranged to advance a shaped specimen through an array of dies that create a shaped orifice with the spacing formed between the dies. These dies segments act under the influence of a powered unit to move in a reciprocating motion that causes the spacings between segments to increase and decrease synchronously thereby shaping the metal segments.
    Type: Application
    Filed: August 28, 2023
    Publication date: December 21, 2023
    Applicant: LeTourneau University
    Inventors: Adam Stroud, Mark Bordelon
  • Publication number: 20070187803
    Abstract: A method of forming a plasma enhanced deposited oxide film on a substrate includes introducing into a chamber containing the substrate silane gas and a dopant gas such as phosphine. The chamber is pressurized and energy is applied to create a plasma. The energy may be a dual frequency energy. The gas rates and pressure are selected to produce a plasma enhanced deposited oxide film on a substrate having a Si—O—Si bond peak absorbance in the IR spectrum of at least 1092 cm?1.
    Type: Application
    Filed: April 25, 2007
    Publication date: August 16, 2007
    Applicant: INTERSIL AMERICAS INC.
    Inventors: Katie Pentas, Mark Bordelon, Jack Linn
  • Publication number: 20060001127
    Abstract: A method of forming a plasma enhanced deposited oxide film on a substrate includes introducing into a chamber containing the substrate silane gas and a dopant gas such as phosphine. The chamber is pressurized and energy is applied to create a plasma. The energy may be a dual frequency energy. The gas rates and pressure are selected to porduce a plasma enhanced deposited oxide film on a substrate having a Si—O—Si bond peak absorbance in the IR spectrum of at least 1092 cm?1.
    Type: Application
    Filed: September 30, 2004
    Publication date: January 5, 2006
    Inventors: Katie Pentas, Mark Bordelon, Jack Linn
  • Patent number: 4958212
    Abstract: An improved memory cell layout (54) is formed including a trench cell (60) formed in a semiconductor substrate (58). The memory cell layout (54) includes a bitline (56) and a wordline (62) for storing and accessing charge. The charge is stored on a capacitor formed from a conductor (68), an insulating region (70) and a semiconductor substrate (58). Bitline (56) is primarily tangential to a trench cell (60), or may surround the periphery thereof. A wordline (62) overlies trench cell (60) and extends therein, and further may be formed of a width narrower than trench cell (60).
    Type: Grant
    Filed: December 30, 1988
    Date of Patent: September 18, 1990
    Assignee: Texas Instruments Incorporated
    Inventors: Clarence W. Teng, William F. Richardson, Robert R. Doering, Ashwin H. Shah, Bing W. Shen, Mark Bordelon