Abstract: Electronic devices coupled to a network may exchange messages containing time-of-day information synchronization of the internal clocks. The information exchanged may include the instant at which a message leaves the electronic device. Discussed herein are methods and systems that allow 1-step timestamping of messages containing time-of-day information. The 1-step timestamping methods and systems may reduce the impact of non-deterministic time delays in the transmit path (e.g., encryption, expansion, inclusion of tags), and may improve the accuracy of the time-of-day information of the packets. For example, systems and methods may allow accurate 1-step timestamping of IEEE 1588 Precision Time Protocol packets with the uncertainty of delays from MACSec encryption or other security mechanisms. Some embodiments employ estimation non-deterministic delay of previously transmitted packets to estimate the state of the transmit path.

Abstract: Examples described herein relate to multiple processor nodes which are physically separate with interfaces to a common network interface. A local processor can run a timing recovery algorithm, and tune the master timer to align with the network domain to cause the master timer and network timing domains to be in the same domain. A common master timer can be used to align time stamps of independent processor nodes. A processor node can use the common master timer as a reference and the processor does not need to communicate with another processor to synchronize its timer.

Abstract: Disclosed herein are systems and methods for initializing and synchronizing a protected real time clock via hardware connections. For example, in some embodiments, a protected real time clock on a trusted execution environment may initialize via a hardware connection to a master clock, which is synchronized to a trusted time source via a hardware connection. In some embodiments, a protected real time clock on a trusted execution environment may initialize to a master clock during a system hardware reset sequence. In some embodiments, before a system is running normally, a real time clock on an integrated Intellectual Property agent may initialize and synchronize to a protected real time clock via a hardware connection. In some embodiments, after a system is running normally, a real time clock on a discrete device may initialize and synchronize to a protected real time clock via a hardware connection.

Abstract: In a transceiver, the accuracy of a packet time stamp can be improved by compensating for errors introduced by processing of the packet. A received packet can be received via multiple lanes. A packet time stamp can be measured using a start of frame delimiter (SFD). A last arriving lane can be used to provide a recovered clock signal. A phase offset between the recovered clock signal and the system clock of the transceiver can be used to adjust the time stamp. A position of the SFD within a data block can be used to adjust the time stamp. A position of the data block within a combined group of data blocks can be used to adjust the time stamp. Also, a serializer-deserializer delay associated with the last arriving lane can be used to adjust the time stamp.

Abstract: Electronic devices coupled to a network may exchange messages containing time-of-day information synchronization of the internal clocks. The information exchanged may include the instant at which a message leaves the electronic device. Discussed herein are methods and systems that allow 1-step timestamping of messages containing time-of-day information. The 1-step timestamping methods and systems may reduce the impact of non-deterministic time delays in the transmit path (e.g., encryption, expansion, inclusion of tags), and may improve the accuracy of the time-of-day information of the packets. For example, systems and methods may allow accurate 1-step timestamping of IEEE 1588 Precision Time Protocol packets with the uncertainty of delays from MACSec encryption or other security mechanisms. Some embodiments employ estimation non-deterministic delay of previously transmitted packets to estimate the state of the transmit path.

Abstract: Technologies for timestamping data packets with forward error correction is disclosed. Alignment markers may be inserted in a data stream in order to assist with synchronization on the receiving end. After insertion of the alignment markers, a start of frame delimiter or other trigger may be detected, triggering a timestamp corresponding to the start of frame delimiter or other trigger. The data and the timestamp are sent to a remote compute device, which may timestamp the data before removing the alignment markers. With this approach, insertion of the alignment markers does not lead to a deviation in the timestamp of the sending compute device or the receiving compute device.

Abstract: Disclosed herein are systems and methods for initializing and synchronizing a protected real time clock via hardware connections. For example, in some embodiments, a protected real time clock on a trusted execution environment may initialize via a hardware connection to a master clock, which is synchronized to a trusted time source via a hardware connection. In some embodiments, a protected real time clock on a trusted execution environment may initialize to a master clock during a system hardware reset sequence. In some embodiments, before a system is running normally, a real time clock on an integrated Intellectual Property agent may initialize and synchronize to a protected real time clock via a hardware connection. In some embodiments, after a system is running normally, a real time clock on a discrete device may initialize and synchronize to a protected real time clock via a hardware connection.

Abstract: Described embodiments provide for a reassembly system for processing an asynchronous transfer mode (ATM) cell of data into an ATM adaptation layer (AAL) packet. A preprocessor module identifies a first conversation identification of one or more minipackets in the ATM cell, and reassembles the one or more minipackets having the first conversation identification into a portion of the AAL packet. A preprocessor determines if a trigger has occurred. In response to a trigger, the preprocessor sends a portion of the reassembled minipackets having the first conversation identification to a destination processor.

Abstract: An apparatus includes a synchronization block and a physical coding sublayer block. The synchronization block may be configured to determine a position of a start of frame delimiter. The physical coding sublayer block may be configured to measure a delay through the physical coding sublayer block and provide delay and delay variation compensation based upon the measured delay.

Abstract: A network processor is described that includes a network reference clock processor module for providing an at least substantially low-jitter, low-wander reference signal. In one or more embodiments, the network reference clock processor module includes a digital phase locked loop configured to at least substantially attenuate a wander noise portion from a reference signal. The network reference clock processor module also includes an analog phase locked loop communicatively coupled to the digital phase locked loop and configured to receive the reference signal from the digital phase locked loop. The analog phase locked loop is configured to attenuate a jitter noise portion having a first frequency characteristic from the reference signal and to provide the reference signal to a transceiver communicatively coupled to the analog phase locked loop. The transceiver is configured to attenuate a jitter noise portion having a second frequency characteristic from the reference signal.

Abstract: Described embodiments provide for a reassembly system for processing an asynchronous transfer mode (ATM) cell of data into an ATM adaptation layer (AAL) packet. A preprocessor module identifies a first conversation identification of one or more minipackets in the ATM cell, and reassembles the one or more minipackets having the first conversation identification into a portion of the AAL packet. A preprocessor determines if a trigger has occurred. In response to a trigger, the preprocessor sends a portion of the reassembled minipackets having the first conversation identification to a destination processor.

Abstract: Methods and apparatus are provided for circuit emulation services over cell and packet networks. A constant bit rate traffic stream is mapped to one of a cell and packet structure. The constant bit rate traffic stream is mapped to one or more cells and the one or more cells are selectively translated to one or more packets if a packet stream is selected. In addition, one of a received cell and packet stream are mapped to a constant bit rate traffic stream. The packet stream is selectively translated to one or more cells and the one or more cells are translated to the constant bit rate traffic stream. A clock can optionally be recovered from the received cell or packet stream.

Abstract: Data traffic of at least one cell stream of a circuit-switched network is processed for transmission over a packet service of a packet-switched network. At least one processor of a communication system node receives data traffic associated with a plurality of virtual circuits of the cell stream, maps the plurality of virtual circuits as a single unit to an identifier of a particular packet service of the packet-switched network, and transmits the data traffic associated with the virtual circuits over the particular packet service. The mapping of the plurality of virtual circuits as a single unit is implemented without requiring any processing of virtual channel indicators of the respective virtual circuits.

Abstract: A method is disclosed for controlling the flow of packets aggregated from multiple logical ports over a transport link. A directed flow control indicator is provided to the transmitting end station that causes a detected congestion condition. The directed flow control indicator causes the transmitting end station to suspend the transmission of further packets. The linear expansion header of the Generic Framing Procedure (GFP) linear mapping scheme is extended to include the flow control indicator, such as a bit indicating a potential overload condition. A directed flow control indication can be provided in one or more packets sent to the transmitting end station over the transport network without increasing the network overhead. If packets are not being sent to the appropriate transmitting end station, a packet generator can generate one or more packets with the flow control indicator to inform the appropriate transmitting end station of the congestion condition.

Abstract: A method and apparatus are disclosed for compensating for a frequency offset between an ingress local area network and an egress local area network that communicate over a transport network. The bandwidth of an egress port is adjusted by varying an inter-packet gap size between each packet so that the packets can be delivered without overflowing an egress buffer. The size of the inter-packet gap is reduced when the frequency of the ingress local area network is greater than the frequency of the egress local area network. The size of the inter-packet gap is increased when the frequency of the ingress local area network is less than the frequency of the egress local area network. The size of the egress inter-packet gap may be statically or dynamically adjusted to compensate for a frequency offset.

Abstract: A method is disclosed for controlling the flow of packets aggregated from multiple logical ports over a transport link. A directed flow control indicator is provided to the transmitting end station that causes a detected congestion condition. The directed flow control indicator causes the transmitting end station to suspend the transmission of further packets. The linear expansion header of the Generic Framing Procedure (GFP) linear mapping scheme is extended to include the flow control indicator, such as a bit that is set to a predefined binary value to indicate a potential overload condition. A directed flow control indication can be provided in one or more packets that are sent to the transmitting end station over the transport network without increasing the network overhead.

Abstract: Methods and apparatus are provided for circuit emulation services over cell and packet networks. A constant bit rate traffic stream is mapped to one of a cell and packet structure. The constant bit rate traffic stream is mapped to one or more cells and the one or more cells are selectively translated to one or more packets if a packet stream is selected. In addition, one of a received cell and packet stream are mapped to a constant bit rate traffic stream. The packet stream is selectively translated to one or more cells and the one or more cells are translated to the constant bit rate traffic stream. A clock can optionally be recovered from the received cell or packet stream.

Abstract: A method and apparatus are disclosed for per-service flow protection and restoration of data in one or more packet networks. The disclosed protection and restoration techniques allow traffic to be prioritized and protected from the aggregate level down to a micro-flow level. Thus, protection can be limited to those services that are fault sensitive. Protected data is duplicated over a primary path and one or more backup data paths. Following a link failure, protected data can be quickly and efficiently restored without significant service interruption. A received packet is classified at each end point based on information in a header portion of the packet, using one or more rules that determine whether the received packet should be protected. At an ingress node, if the packet classification determines that the received packet should be protected, then the received packet is transmitted on at least two paths.

Abstract: A method and apparatus are disclosed for compensating for a frequency offset between an ingress local area network and an egress local area network that communicate over a transport network. The bandwidth of an egress port is adjusted by varying an inter-packet gap size between each packet so that the packets can be delivered without overflowing an egress buffer. The size of the inter-packet gap is reduced when the frequency of the ingress local area network is greater than the frequency of the egress local area network. The size of the inter-packet gap is increased when the frequency of the ingress local area network is less than the frequency of the egress local area network. The size of the egress inter-packet gap may be statically or dynamically adjusted to compensate for a frequency offset.

Abstract: A method is disclosed for controlling the flow of packets aggregated from multiple logical ports over a transport link. A directed flow control indicator is provided to the transmitting end station that causes a detected congestion condition. The directed flow control indicator causes the transmitting end station to suspend the transmission of further packets. The linear expansion header of the Generic Framing Procedure (GFP) linear mapping scheme is extended to include the flow control indicator, such as a bit that is set to a predefined binary value to indicate a potential overload condition. A directed flow control indication can be provided in one or more packets that are sent to the transmitting end station over the transport network without increasing the network overhead.