Patents by Inventor Mark Bossard
Mark Bossard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240104254Abstract: A system and associated methodology for predictive construction cost estimation. Path data, extracted from a vector-based data source, is decoded and correlated into a point-map-to-line-segment array providing the ability to predictively snap a cursor on a user interface to points and/or line segments illustrated in the vector-based data source. Once identified and committed to by the user, the invention thereafter links additional snapped points/line segments/polylines enabling the user to quickly and efficient move throughout the data source crating a timely and accurate construction estimation.Type: ApplicationFiled: September 12, 2023Publication date: March 28, 2024Applicant: eTakeoff LLCInventors: Mark A Bossard, David L Snedaker, Matthew W Spaulding
-
Patent number: 11790122Abstract: A system and associated methodology for predictive construction cost estimation. Path data, extracted from a vector-based data source, is decoded and correlated into a point-map-to-line-segment array providing the ability to predictively snap a cursor on a user interface to points and/or line segments illustrated in the vector-based data source. Once identified and committed to by the user, the invention thereafter links additional snapped points/line segments/polylines enabling the user to quickly and efficient move throughout the data source crating a timely and accurate construction estimation.Type: GrantFiled: October 29, 2021Date of Patent: October 17, 2023Assignee: ETAKEOFF, LLC.Inventors: Mark A. Bossard, David L. Snedaker, Matthew W. Spaulding
-
Publication number: 20220138361Abstract: A system and associated methodology for predictive construction cost estimation. Path data, extracted from a vector-based data source, is decoded and correlated into a point-map-to-line-segment array providing the ability to predictively snap a cursor on a user interface to points and/or line segments illustrated in the vector-based data source. Once identified and committed to by the user, the invention thereafter links additional snapped points/line segments/polylines enabling the user to quickly and efficient move throughout the data source crating a timely and accurate construction estimation.Type: ApplicationFiled: October 29, 2021Publication date: May 5, 2022Applicant: eTakeoff LLCInventors: Mark A. Bossard, David L. Snedaker, Matthew W. Spaulding
-
Patent number: 8193846Abstract: A programmable pulse generator having a clock signal delay chain, multiplexer, and reduced voltage charge circuit. The clock delay chain comprises a plurality of propagated delays, coupled to the multiplexer. The multiplexer selects a particular clock delay signal from a plurality of delay chain taps. The multiplexer is driven by a tap select register coupled to a state machine. The state machine controls the programmable pulse output, encoding the data by varying the pulse width and delay between pulses. The delay of pulse outputs from the multiplexer are reduced by coupling a reduced voltage pre-charge circuit to the multiplexer.Type: GrantFiled: July 27, 2009Date of Patent: June 5, 2012Assignee: Atmel CorporationInventors: John L. Fagan, Mark Bossard
-
Publication number: 20090284296Abstract: A programmable pulse generator having a clock signal delay chain, multiplexer, and reduced voltage charge circuit. The clock delay chain comprises a plurality of propagated delays, coupled to the multiplexer. The multiplexer selects a particular clock delay signal from a plurality of delay chain taps. The multiplexer is driven by a tap select register coupled to a state machine. The state machine controls the programmable pulse output, encoding the data by varying the pulse width and delay between pulses. The delay of pulse outputs from the multiplexer are reduced by coupling a reduced voltage pre-charge circuit to the multiplexer.Type: ApplicationFiled: July 27, 2009Publication date: November 19, 2009Applicant: Atmel CorporationInventors: John L. Fagan, Mark A. Bossard
-
Patent number: 7471132Abstract: An electronic device selects one of a plurality of input signals for coupling to an output channel. Individual pulldowns provide a separate pathway for each input, and are coupled to a common node which: is pre-charged to a voltage less than a system voltage. Each pulldown is coupled to a select line for gating an associated input signal.Type: GrantFiled: November 14, 2006Date of Patent: December 30, 2008Assignee: Atmel CorporationInventors: John L. Fagan, Mark A. Bossard
-
Patent number: 7233185Abstract: A vernier time shifting circuit is used for fine-tuning capture of a clock signal and/or a data signal to compensate for fluctuations produced by the system or other variations within non-time invariant parts of the chip. Other variations can include process, temperature, or voltage differences. The vernier sample time shifting circuit allows shifting the signal in small steps to allow for optimal sampling.Type: GrantFiled: April 29, 2004Date of Patent: June 19, 2007Assignee: Atmel CorporationInventors: John L. Fagan, Mark A. Bossard, Daniel S. Cohen
-
Publication number: 20070069785Abstract: An electronic device selects one of a plurality of input signals for coupling to an output channel. Individual pulldowns provide a separate pathway for each input, and are coupled to a common node which: is pre-charged to a voltage less than a system voltage. Each pulldown is coupled to a select line for gating an associated input signal.Type: ApplicationFiled: November 14, 2006Publication date: March 29, 2007Applicant: ATMEL CORPORATIONInventors: John Fagan, Mark Bossard
-
Patent number: 7157958Abstract: An electronic device selects one of a plurality of input signals for coupling to an output channel. Individual pulldowns provide a separate pathway for each input, and are coupled to a common node which is pre-charged to a voltage less than a system voltage. Each pulldown is coupled to a select line for gating an associated input signal.Type: GrantFiled: October 8, 2004Date of Patent: January 2, 2007Assignee: Atmel CorporationInventors: John L. Fagan, Mark A. Bossard
-
Patent number: 7103110Abstract: An dual phase pulse modulation (DPPM) encoder circuit converts data into a series of high and low signal pulses, each of whose time durations or pulse widths represents a group of M data bits, with the alternating high and low pulses representing successive groups. The encoder circuit may include a set of parallel-in, serial-out shift registers that subdivide received data words into the M-bit groups, a state machine that specified the pulse durations for each received group, e.g., by incrementing a state that indicates selected signal pulse transition times, a system clock delay chain with multiple taps, a multiplexer controlled by the state machine for successively selecting different taps, and a toggle flip-flop that is clocked by the multiplexer output.Type: GrantFiled: April 29, 2004Date of Patent: September 5, 2006Assignee: Atmel CorporationInventors: Daniel S. Cohen, John L. Fagan, Mark A. Bossard
-
Publication number: 20050077939Abstract: An electronic device selects one of a plurality of input signals for coupling to an output channel. Individual pulldowns provide a separate pathway for each input, and are coupled to a common node which is pre-charged to a voltage less than a system voltage. Each pulldown is coupled to a select line for gating an associated input signal.Type: ApplicationFiled: October 8, 2004Publication date: April 14, 2005Inventors: John Fagan, Mark Bossard
-
Publication number: 20050078021Abstract: An dual phase pulse modulation (DPPM) encoder circuit converts data into a series of high and low signal pulses, each of whose time durations or pulse widths represents a group of M data bits, with the alternating high and low pulses representing successive groups. The encoder circuit may include a set of parallel-in, serial-out shift registers that subdivide received data words into the M-bit groups, a state machine that specified the pulse durations for each received group, e.g., by incrementing a state that indicates selected signal pulse transition times, a system clock delay chain with multiple taps, a multiplexer controlled by the state machine for successively selecting different taps, and a toggle flip-flop that is clocked by the multiplexer output.Type: ApplicationFiled: April 29, 2004Publication date: April 14, 2005Inventors: Daniel Cohen, John Fagan, Mark Bossard
-
Publication number: 20050077942Abstract: A vernier time shifting circuit is used for fine-tuning capture of a clock signal and/or a data signal to compensate for fluctuations produced by the system or other variations within non-time invariant parts of the chip. Other variations can include process, temperature, or voltage differences. The vernier sample time shifting circuit allows shifting the signal in small steps to allow for optimal sampling.Type: ApplicationFiled: April 29, 2004Publication date: April 14, 2005Inventors: John Fagan, Mark Bossard, Daniel Cohen
-
Publication number: 20050077941Abstract: A programmable pulse generator having a clock signal delay chain, multiplexer, and reduced voltage charge circuit. The clock delay chain comprises a plurality of propagated delays, coupled to the multiplexer. The multiplexer selects a particular clock delay signal from a plurality of delay chain taps. The multiplexer is driven by a tap select register coupled to a state machine. The state machine controls the programmable pulse output, encoding the data by varying the pulse width and delay between pulses. The delay of pulse outputs from the multiplexer are reduced by coupling a reduced voltage pre-charge circuit to the multiplexer.Type: ApplicationFiled: October 8, 2004Publication date: April 14, 2005Inventors: John Fagan, Mark Bossard