Abstract: A current mode pipelined analogue to digital converter (ADC) has a plurality of serially connected conversion stages. Each conversion stage has an input (40) for receiving a sampled and held current which is connected via a switch (S41) to a first current memory (M42) and via a switch (S40) to a second current memory (M41). The output of the second current memory (M41) is fed via a switch (S44) to one input of a summing junction (46). The output of the first current memory (M42) is fed via a switch (S42) to the input of a comparator (L44) whose output is clocked into a latch (L44) whose Q output is connected to an output (45) as the digital result of the conversion. The Q output of the latch (L44) is also connected to a digital to analogue converter (46) whose analogue output is fed to a second input of the summing junction 46 via a switch (S43) to form the analogue residue signal for application via output (47) to the next conversion stage in the pipeline.

Abstract: A digital to anologue converter comprises a plurality of current sources (T.sub.o -T.sub.n) and corresponding selection switches (D.sub.o -D.sub.n) which connect the current sources to an output (3). In order to enable a constant capacitance to be presented at the output (3) regardless of the input digital code a plurality of dummy current sources (T.sub.o -T.sub.n) which take the same form as the current sources (To-T.sub.n) are provided. The dummy current sources have associated selection switches ( D.sub.o -D.sub.n) which are operated by the logical inverse of the code applied to the current sources (T.sub.o -T.sub.n).

Abstract: A current comparator arrangement has first and second inputs (100, 103), an output (105), and cross-coupled transistors (MP1, MP2) which form a latching circuit. The arrangement also includes current stores (MP3, MP4), the input currents to be compared being fed to the current stores in a selected forward differential order for storage therein during a first portion of a clock period in which the cross-coupled latching circuit is reset. During a second portion of the clock period the input current connections are reversed, thereby reversing their differential order, and the reverse order currents are supplied together with the stored forward order currents to the latching circuit. This cancels common mode and offset currents so that they do not affect the comparison of the input currents.