Patents by Inventor Mark Bradley

Mark Bradley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190361071
    Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.
    Type: Application
    Filed: July 16, 2019
    Publication date: November 28, 2019
    Inventors: Edward John Coyne, Alan J. O'Donnell, Shaun Bradley, David Aherne, David Boland, Thomas G. O'Dwyer, Colm Patrick Heffernan, Kevin B. Manning, Mark Forde, David J. Clarke, Michael A. Looby
  • Patent number: 10475241
    Abstract: Super-resolution displays, and methods of operating the same are disclosed herein. An example disclosed method includes emitting light from a pixel at a first location in a display assembly, and emitting light from the pixel at a second different location in the display assembly.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: November 12, 2019
    Assignee: GOOGLE LLC
    Inventors: Martin Friedrich Schubert, Mark Bradley Spitzer
  • Patent number: 10469403
    Abstract: Embodiments can provide additional computing resources at minimal and incremental cost by providing instances of one or more server compute subsystems on a system-on-chip. The system-on-chip can include multiple compute subsystems where each compute subsystem can include dedicated processing and memory resources. The system-on-chip can also include a management compute subsystem that can manage the processing and memory resources for each subsystem.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: November 5, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Mark Bradley Davis, David James Borland
  • Publication number: 20190332840
    Abstract: The parameters of an optical code are optimized to achieve improved signal robustness, reliability, capacity and/or visual quality. An optimization program can determine spatial density, dot distance, dot size and signal component priority to optimize robustness. An optical code generator employs these parameters to produce an optical code at the desired spatial density and robustness. The optical code is merged into a host image, such as imagery, text and graphics of a package or label, or it may be printed by itself, e.g., on an otherwise blank label or carton. A great number of other features and arrangements are also detailed.
    Type: Application
    Filed: May 7, 2019
    Publication date: October 31, 2019
    Inventors: Ravi K. Sharma, Tomas Denemark, Brett A. Bradley, Geoffrey B. Rhoads, Eoin C. Sinclair, Vojtech Holub, Hugh L. Brunk, Trent J. Brundage, John F. Stach, John D. Lord, Joel R. Meyer, Tomas Filler, Ajith M. Kamath, Mark-Andrew Ray Tait, Kevin J. Hansonoda, Adnan M. Alattar
  • Patent number: 10451459
    Abstract: There is disclosed inhaler testing apparatus, in which at least one flow regulation valve, such as a needle valve, is located within a conduit. The flow regulation valve divides the conduit into inlet and outlet sides of the valve. The inlet side is arranged for connection to an inhaler and the outlet side for connection to a vacuum source. An electric motor provides variable adjustment of a flow opening through the valve. At least one sensor senses pressure or flow rate in the inlet side and a controller automatically adjusts the flow opening through the valve in response to readings from the at least one sensor. The apparatus may also comprise a shut off valve, such as a solenoid valve.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: October 22, 2019
    Inventors: Mark Andrew Copley, Benjamin Bradley, Ian Christopher Evans, Jonathan Charles Stephen Wright
  • Publication number: 20190315569
    Abstract: Disclosed herein is a movable platform (MP) for moving freight during cross-dock operations. The MP comprises a mechanical lift brake assembly that can be utilized to deploy a plurality of mechanical lift brakes preventing further movement of the MP. AMP forklift attachment that can be used to convey the MP and to engage or disengage the mechanical lift brake assembly. The MP forklift attachment can be attached to a conveyance vehicle, such as a forklift, or built into an automated guided vehicle.
    Type: Application
    Filed: June 27, 2019
    Publication date: October 17, 2019
    Inventors: Seth Galewyrick, Patrick Sullivan, Mark Bradley
  • Patent number: 10434191
    Abstract: The present invention relates to methods of visualising cells especially although not exclusively in vivo using a dye, such as a dendrimer-dye molecule or polybranched-dye molecule which is internalised by the cells and thus permits subsequent visualisation by confocal fluorescence endomicroscopy or other optical detectors. There is also provided internally quenched probes for use in visualising cells especially although not exclusively in vivo by confocal fluorescence endomicroscopy and the use of internally quenched probes in combination with confocal fluorescence endomicroscopy, for visualising cells by virtue of internalisation and dequenching of a probe by the cells. In a particular embodiment the cells are activated neutrophils, such as within the lung of a subject.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: October 8, 2019
    Assignee: THE UNIVERSITY COURT OF THE UNIVERSITY OF EDINBURGH
    Inventors: Tashfeen Walton, Mark Bradley, Kev Dhaliwal, Nikolaos Avlonitis, Chris Haslett, Neil McDonald, Manuelle Debunne
  • Publication number: 20190293715
    Abstract: Methods and apparatus are disclosed for programming reconfigurable logic devices such as FPGAs in a multi-tenant server environment. In one example, a computing host includes one or more processors configured to execute a supervisor process and two or more user processes and a single FPGA integrated circuit configured into a plurality of partitions. The partitions include a host logic partition that is accessible only to the supervisor process executing on the computing host, and two or more accelerator partitions. Each of the accelerator partitions is configured to include a virtual debug unit with a logic analyzer that collects logic signals generated by logic within the respective accelerator partition and sends debug data indicating values of the logic signals to one of the user processes. In some examples, the host logic partitions and/or the accelerator partitions can be independently reprogrammed of each other within their respective portions of the single FPGA.
    Type: Application
    Filed: May 24, 2019
    Publication date: September 26, 2019
    Applicant: Amazon Technologies, Inc.
    Inventors: Mark Bradley Davis, Christopher Joseph Pettey, Asif Khan, Islam Mohamed Hatem Abdulfattah Mohamed Atta
  • Publication number: 20190290800
    Abstract: The present invention relates to a polymer having a first monomer selected from the group consisting of: styrene, MMA, HEMA or MEMA and a second monomer selected from the group consisting of: GMA, DEAEA, DEAEMA, DMAA, BAEMA, 4-vinylpyridine, DMVBA, 1-vinylimidazole, DMAEA or a combination thereof as coating agent for a scaffold or a medical device, to promote cellular adhesion and/or cell growth or for the manufacture of yarns or threads. The polymer may further contain a third monomer selected from the group consisting of: BMA, DEGMEMA, DAAA and MMA. The invention also relates to a scaffold, a medical device, a yarn, a thread or a textile coated or manufactured with the polymers of the invention and relative methods.
    Type: Application
    Filed: March 17, 2017
    Publication date: September 26, 2019
    Inventors: Maurizio PESCE, Rosaria SANTORO, Mark BRADLEY, Seshasailam VENKATESWARAN
  • Patent number: 10423438
    Abstract: In a multi-tenant environment, separate virtual machines can be used for configuring and operating different subsets of programmable integrated circuits, such as a Field Programmable Gate Array (FPGA). The programmable integrated circuits can communicate directly with each other within a subset, but cannot communicate between subsets. Generally, all of the subsets of programmable ICs are within a same host server computer within the multi-tenant environment, and are sandboxed or otherwise isolated from each other so that multiple customers can share the resources of the host server computer without knowledge or interference with other customers.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: September 24, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Islam Mohamed Hatem Abdulfattah Mohamed Atta, Mark Bradley Davis, Robert Michael Johnson, Christopher Joseph Pettey, Asif Khan, Nafea Bshara
  • Patent number: 10394731
    Abstract: Embodiments of the technology can provide the flexibility of fine-grained dynamic partitioning of various compute resources among different compute subsystems on an SoC. A plurality of processing cores, cache hierarchies, memory controllers and I/O resources can be dynamically partitioned between a network compute subsystem and a server compute subsystem on the SoC.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: August 27, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Mark Bradley Davis, David James Borland
  • Publication number: 20190256250
    Abstract: Disclosed herein is a modular deck system that utilizes a combination of a movable platform having a plurality of vertical posts with engagement members. Decks, filled with freight, can be placed onto the vertical posts at various heights at different sections of the movable platform using a conveyance vehicle. Further, the height of the vertical posts can be extended using an extension post for securing tall cargo. The decks can also be locked to the vertical posts to prevent dislodgement of the deck during transport of the movable platform.
    Type: Application
    Filed: May 7, 2019
    Publication date: August 22, 2019
    Inventors: Mark Bradley, Patrick Sullivan, Shannon Lively, Seth Galewyrick, Stonie Hopkins, Dylan Henderson, Brad Blackstone
  • Publication number: 20190258597
    Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.
    Type: Application
    Filed: February 27, 2019
    Publication date: August 22, 2019
    Inventors: Islam Atta, Christopher Joseph Pettey, Asif Khan, Robert Michael Johnson, Mark Bradley Davis, Erez Izenberg, Nafea Bshara, Kypros Constantinides
  • Patent number: 10370191
    Abstract: Disclosed herein is a movable platform (MP) for moving freight during cross-dock operations. The MP comprises a mechanical lift brake assembly that can be utilized to deploy a plurality of mechanical lift brakes preventing further movement of the MP. AMP forklift attachment that can be used to convey the MP and to engage or disengage the mechanical lift brake assembly. The MP forklift attachment can be attached to a conveyance vehicle, such as a forklift, or built into an automated guided vehicle.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: August 6, 2019
    Assignee: INNOVATIVE LOGISTICS, INC.
    Inventors: Seth Galewyrick, Patrick Sullivan, Mark Bradley
  • Patent number: 10365322
    Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: July 30, 2019
    Assignee: ANALOG DEVICES GLOBAL
    Inventors: Edward John Coyne, Alan J. O'Donnell, Shaun Bradley, David Aherne, David Boland, Thomas G. O'Dwyer, Colm Patrick Heffernan, Kevin B. Manning, Mark Forde, David J. Clarke, Michael A. Looby
  • Patent number: 10353843
    Abstract: A device can include one of more configurable packet processing pipelines to process a plurality of packets. Each configurable packet processing pipeline can include a plurality of packet processing components, wherein each packet processing component is configured to perform one or more packet processing operations for the device. The plurality of packet processing components are coupled to a packet processing interconnect, wherein each packet processing component is configured to route the packets through the packet processing interconnect for the one or more configurable packet processing pipelines.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: July 16, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Mark Bradley Davis, Asif Khan, Thomas A. Volpe, Robert Michael Johnson
  • Publication number: 20190210098
    Abstract: An apparatus for continuous casting metal strip reducing snake eggs comprising a pair of counter rotating casting rolls, each roll less than 800 millimeters in diameter and positioned to form a nip there between through which thin strip can be cast; a metal delivery system disposed above the nip and capable of discharging molten metal to form a casting pool supported on the rolls; a pair of side dam holders and a pair of side dams assembled adjacent each end portion of the rolls, each side dam holder tapered along edge portions to dovetail with an adjacent side dam, and each side dam adapted to confine the casting pool of molten metal supported on casting surfaces of the rolls; an oscillation mechanism adapted to cause lateral oscillation of each side dam and side dam holder at a frequency 2-50 hertz and with an amplitude 100-2000 ?m during a casting campaign.
    Type: Application
    Filed: August 10, 2017
    Publication date: July 11, 2019
    Inventors: Mark SCHLICHTING, Volus MCKENNA, Alan DENO, James M. THOMAS, Philippe Maurice FETTIG, Harold Bradley REES, Nick COREA, Michael PONDER
  • Publication number: 20190213155
    Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a plurality of reconfigurable logic regions. Each reconfigurable region can include hardware that is configurable to implement an application logic design. The host logic can be used for separately encapsulating each of the reconfigurable logic regions. The host logic can include a plurality of data path functions where each data path function can include a layer for formatting data transfers between a host interface and the application logic of a corresponding reconfigurable logic region. The host interface can be configured to apportion bandwidth of the data transfers generated by the application logic of the respective reconfigurable logic regions.
    Type: Application
    Filed: March 21, 2019
    Publication date: July 11, 2019
    Applicant: Amazon Technologies, Inc.
    Inventors: Asif Khan, Islam Mohamed Hatem Abdulfattah Mohamed Atta, Robert Michael Johnson, Mark Bradley Davis, Christopher Joseph Pettey, Nafea Bshara, Erez Izenberg
  • Patent number: 10346342
    Abstract: A plurality of system on chips (SoCs) in a server computer can be coupled to a plurality of memory agents (MAs) via respective Serializer/Deserializer (SerDes) interfaces. Each of the plurality of MAs can include one or more memory controllers to communicate with a memory coupled to the respective MA, and globally addressable by each of the SoCs. Each of the plurality of SoCs can access the memory coupled to any of the MAs in uniform number of hops using the respective SerDes interfaces. Different types of memories, e.g., volatile memory, persistent memory, can be supported.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: July 9, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Mark Bradley Davis, Thomas A. Volpe, Nafea Bshara, Yaniv Shapira, Adi Habusha
  • Patent number: 10338135
    Abstract: Methods and apparatus are disclosed for programming reconfigurable logic devices such as FPGAs in a multi-tenant server environment. In one example, a computing host includes one or more processors configured to execute a supervisor process and two or more user processes and a single FPGA integrated circuit configured into a plurality of partitions. The partitions include a host logic partition that is accessible only to the supervisor process executing on the computing host, and two or more accelerator partitions. Each of the accelerator partitions is configured to include a virtual debug unit with a logic analyzer that collects logic signals generated by logic within the respective accelerator partition and sends debug data indicating values of the logic signals to one of the user processes. In some examples, the host logic partitions and/or the accelerator partitions can be independently reprogrammed of each other within their respective portions of the single FPGA.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: July 2, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Mark Bradley Davis, Christopher Joseph Pettey, Asif Khan, Islam Mohamed Hatem Abdulfattah Mohamed Atta