Abstract: A method and an apparatus for measuring insulating film thickness, such as the width of sidewall spacers. The method includes positioning a first test structure having a first resistance at a first location on a semiconductor wafer and positioning a second test structure having a second resistance different from the first resistance at a second location on the semiconductor wafer. The method also includes measuring the first resistance of the first test structure and measuring the second resistance of the second test structure. The method also includes determining an average characteristic of the first test structure and the second test structure, other than resistance, based on the first resistance of the first test structure and the second resistance of the second test structure.

Abstract: An apparatus and method for verifying a process step in the fabrication of an integrated circuit device is implemented. A ring oscillator is fabricated on the dice constituting the integrated circuit device being manufactured. The ring oscillator structure is adapted for sensitizing the ring oscillator to variations in the process step being verified. During test of the wafer containing the dice, a scan of the frequency of the ring oscillator across the wafer for each die under test is made. Deviations in the ring oscillator frequency from a preselected nominal value delimit regions of the wafer for which the process step is marginal.

Abstract: The present invention is directed to a method that comprises forming a plurality of transistors, each transistor having at least a gate electrode, and forming halo implant regions in the transistors while varying at least one of a halo implant angle, a masking layer height, and a lateral offset of a masking layer from the gate electrode of the transistors. The method further comprises determining electrical performance characteristics of at least some of the transistors where at least one of the halo implant angle, the masking layer height, and the lateral offset of a masking layer are different, and comparing the determined electrical performance characteristics of the transistors.

Abstract: An apparatus and method for detecting speed variations across a die, a flash field, i.e., multiple dies, and multiple flash fields. In one embodiment, a method comprises the step of inserting a plurality of functional circuits at strategic locations across a die or flash field or multiple flash fields where each of the plurality of functional circuits generates data, e.g., values, frequency, etc., correlated to the die speeds at the strategic locations. The method further comprises reading the data generated by the plurality of functional circuits that may be correlated to the die speeds at the strategic locations. Speed variations across the die or flash field or multiple flash fields may then be subsequently detected based on the data generated by the plurality of functional circuits. Upon analyzing the data generated by the plurality of functional circuits, adjustments may be made to the manufacturing process to improve the number of acceptable integrated circuits or chips disposed in the dies.

Abstract: A method for electrically quantifying a semiconductor device's spacers' width. In one embodiment, a method comprises the step of measuring a resistance across a region of interest of each of a plurality of semiconductor structures including the semiconductor device in question, where the region of interest may be a source or drain region of the semiconductor structure or may be one of a plurality of lightly doped drain regions of the semiconductor structure. The method further comprises determining a width of one of a plurality of lightly doped drain regions of the semiconductor device from the resistance across the region of interest of each of the plurality of semiconductor structures. The method further comprises determining the semiconductor device's spacers' width from the width of one of the plurality of lightly doped drain regions of the semiconductor device.