Patents by Inventor Mark Buxton
Mark Buxton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200228801Abstract: Techniques related to parallel block video coding using an adaptive wavefront split are discussed. Such techniques include adaptively applying a wavefront split in a video frame based on a frame level quantization parameter of the video frame, an encode duration of a previous frame, and/or image content of the video frame.Type: ApplicationFiled: March 24, 2020Publication date: July 16, 2020Applicant: INTEL CORPORATIONInventors: Jason Tanner, Sergei Plotnikov, Mark Buxton
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Patent number: 10146536Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.Type: GrantFiled: January 31, 2018Date of Patent: December 4, 2018Assignee: Intel CorporationInventors: Rajiv Kapoor, Ronen Zohar, Mark Buxton, Zeev Sperber, Koby Gottlieb
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Publication number: 20180181395Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.Type: ApplicationFiled: January 31, 2018Publication date: June 28, 2018Inventors: Rajiv Kapoor, Ronen Zohar, Mark Buxton, Zeev Sperber, Koby Gottlieb
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Patent number: 9962794Abstract: A flux cored welding electrode for welding a 5-9% nickel steel workpiece by a flux cored arc welding (FCAW) process comprises a particulate core and a metal sheath surrounding the particulate core, wherein chemical composition of the metal sheath and the chemical composition of the particulate core are selected so that the weld deposit composition produced by the welding electrode comprises ?0.15 C, ?6.0 Mn, ?1.0 Si, ?0.025 P, ?0.020 S, 12.0-20.0 Cr, ?55.0 Ni, 5.5-7.5 Mo, 1.2-1.8 Nb+Ta, ?12 Fe, ?0.3 Cu and 0.5-4.0 W.Type: GrantFiled: September 12, 2014Date of Patent: May 8, 2018Assignee: LINCOLN GLOBAL, INC.Inventors: Zhuyao Zhang, Vincent van der Mee, Peter van Erk, Mark Buxton
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Patent number: 9898285Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.Type: GrantFiled: November 7, 2016Date of Patent: February 20, 2018Assignee: Intel CorporationInventors: Rajiv Kapoor, Ronen Zohar, Mark Buxton, Zeev Sperber, Koby Gottlieb
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Publication number: 20170364476Abstract: Method, apparatus, and program means for performing a dot-product operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store to a storage location a result value equal to a dot-product of at least two operands.Type: ApplicationFiled: June 30, 2017Publication date: December 21, 2017Inventors: Ronen Zohar, Mark Seconi, Rajesh Parthasarathy, Srinivas Chennupaty, Mark Buxton, Chuck Desylva, Mohammad Abdallah
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Publication number: 20170161068Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.Type: ApplicationFiled: November 7, 2016Publication date: June 8, 2017Inventors: Rajiv Kapoor, Ronen Zohar, Mark Buxton, Zeev Sperber, Koby Gottlieb
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Patent number: 9489198Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.Type: GrantFiled: February 4, 2016Date of Patent: November 8, 2016Assignee: Intel CorporationInventors: Rajiv Kapoor, Ronen Zohar, Mark Buxton, Zeev Sperber, Koby Gottlieb
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Publication number: 20160154647Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.Type: ApplicationFiled: February 4, 2016Publication date: June 2, 2016Inventors: Rajiv Kapoor, Ronen Zohar, Mark Buxton, Zeev Sperber, Koby Gottlieb
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Patent number: 9268565Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.Type: GrantFiled: April 12, 2015Date of Patent: February 23, 2016Assignee: Intel CorporationInventors: Rajiv Kapoor, Ronen Zohar, Mark Buxton, Zeev Sperber, Koby Gottlieb
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Patent number: 9235415Abstract: In one embodiment, the present invention includes logic to receive a permute instruction, first and second source operands, and control values, and to perform a permute operation based on an operation between at least two of the control values so that selected portions of the first and second source operands or a predetermined value can be stored into elements of a destination. Multiple permute instructions may be combined to perform efficient table lookups. Other embodiments are described and claimed.Type: GrantFiled: November 5, 2014Date of Patent: January 12, 2016Assignee: Intel CorporationInventors: Cristina Anderson, Mark Buxton, Doron Orenstein, Robert Valentine
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Patent number: 9170813Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.Type: GrantFiled: February 8, 2013Date of Patent: October 27, 2015Assignee: Intel CorporationInventors: Rajiv Kapoor, Ronen Zohar, Mark Buxton, Zeev Sperber, Koby Gottlieb
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Publication number: 20150212816Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.Type: ApplicationFiled: April 12, 2015Publication date: July 30, 2015Inventors: Rajiv Kapoor, Ronen Zohar, Mark Buxton, Zeev Sperber, Koby Gottlieb
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Patent number: 9043379Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.Type: GrantFiled: October 19, 2012Date of Patent: May 26, 2015Assignee: Intel CorporationInventors: Rajiv Kapoor, Ronen Zohar, Mark Buxton, Zeev Sperber, Koby Gottlieb
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Patent number: 9037627Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.Type: GrantFiled: February 8, 2013Date of Patent: May 19, 2015Assignee: Intel CorporationInventors: Rajiv Kapoor, Ronen Zohar, Mark Buxton, Zeev Sperber, Koby Gottlieb
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Publication number: 20150076130Abstract: A flux cored welding electrode for welding a 5-9% nickel steel workpiece by a flux cored arc welding (FCAW) process comprises a particulate core and a metal sheath surrounding the particulate core, wherein chemical composition of the metal sheath and the chemical composition of the particulate core are selected so that the weld deposit composition produced by the welding electrode comprises ?0.15 C, ?6.0 Mn, ?1.0 Si, ?0.025 P, ?0.020 S, 12.0-20.0 Cr, ?55.0 Ni, 5.5-7.5 Mo, 1.2-1.8 Nb+Ta, ?12 Fe, ?0.3 Cu and 0.5-4.0 W.Type: ApplicationFiled: September 12, 2014Publication date: March 19, 2015Inventors: Zhuyao Zhang, Vincent van der Mee, Peter van Erk, Mark Buxton
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Publication number: 20150058603Abstract: In one embodiment, the present invention includes logic to receive a permute instruction, first and second source operands, and control values, and to perform a permute operation based on an operation between at least two of the control values so that selected portions of the first and second source operands or a predetermined value can be stored into elements of a destination. Multiple permute instructions may be combined to perform efficient table lookups. Other embodiments are described and claimed.Type: ApplicationFiled: November 5, 2014Publication date: February 26, 2015Inventors: Cristina Anderson, Mark Buxton, Doron Orenstein, Robert Valentine
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Patent number: 8909901Abstract: In one embodiment, the present invention includes logic to receive a permute instruction, first and second source operands, and control values, and to perform a permute operation based on an operation between at least two of the control values so that selected portions of the first and second source operands or a predetermined value can be stored into elements of a destination. Multiple permute instructions may be combined to perform efficient table lookups. Other embodiments are described and claimed.Type: GrantFiled: December 28, 2007Date of Patent: December 9, 2014Assignee: Intel CorporationInventors: Cristina Anderson, Mark Buxton, Doron Orenstien, Bob Valentine
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Publication number: 20140032624Abstract: Method, apparatus, and program means for performing a dot-product operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store to a storage location a result value equal to a dot-product of at least two operands.Type: ApplicationFiled: September 30, 2013Publication date: January 30, 2014Inventors: Ronen Zohar, Mark Seconi, Rajesh Parthasarathy, Srinivas Chennupaty, Mark Buxton, Chuck Desylva
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Publication number: 20140032881Abstract: Method, apparatus, and program means for performing a dot-product operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store to a storage location a result value equal to a dot-product of at least two operands.Type: ApplicationFiled: September 30, 2013Publication date: January 30, 2014Inventors: Ronen Zohar, Mark Seconi, Rajesh Parthasarathy, Srinivas Chennupaty, Mark Buxton, Chuck Desylva