Patents by Inventor Mark C. Davis

Mark C. Davis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11900108
    Abstract: A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: February 13, 2024
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, James D. Guilford, Gilbert M. Wolrich, Wajdi K. Feghali, Erdinc Ozturk, Martin G. Dixon, Sean P. Mirkes, Bret L. Toll, Maxim Loktyukhin, Mark C. Davis, Alexandre J. Farcy
  • Publication number: 20230352464
    Abstract: Embodiments of a microelectronic assembly comprise a first integrated circuit (IC) die including a plurality of first circuits separated by scribe regions, and a plurality of second IC dies coupled to the first IC die, each one of the second IC dies being coupled proximate and adjacent to a corresponding one of the first circuits and conductively coupled to the corresponding one of the first circuits. One or more of the second IC dies comprises a second circuit different from the first circuit, adjacent ones of the first circuits are coupled by a conductive pathway through the corresponding scribe regions, and the first IC die and the second IC die are coupled by interconnects having a pitch not more than 10 micrometers between adjacent interconnects.
    Type: Application
    Filed: April 29, 2022
    Publication date: November 2, 2023
    Applicant: Intel Corporation
    Inventors: Satish Damaraju, Scott E. Siers, Altug Kokar, Wilfred Gomes, Mark C. Davis
  • Publication number: 20230305993
    Abstract: Described herein is a modular parallel processor and associated manufacturing method in which the parallel processor is assembled from multiple chiplets that populate multiple chiplet slots of an active base chiplet die. The multiple chiplets are tested to determine characteristics of the chiplet, such as a number of functional units or a power consumption metric for the chiplet. The multiple chiplet slots can be configured to be populated by one or more chunks of multiple chiplets, where each chunk has a pre-determined collective value. The pre-determined collective value can be a total number of functional execution cores within a chunk or a collective power metric for the chunk.
    Type: Application
    Filed: March 23, 2022
    Publication date: September 28, 2023
    Applicant: Intel Corporation
    Inventors: Mark C. Davis, Ahmed Abou-Alfotouh, Hong Jiang
  • Publication number: 20230305978
    Abstract: Described herein is a modular parallel processor comprising an active base die including hardware logic, interconnect logic, and a plurality of chiplet slots and a plurality of chiplets vertically stacked on the active base die and coupled with the plurality of chiplet slots of the active base die. The plurality of chiplets is interchangeable during assembly of the modular parallel processor and include a group of hardware logic chiplets having a plurality of different functional units and a group of memory chiplets having a plurality of different memory devices. The hardware logic chiplets and the memory chiplets interconnect via the interconnect logic within the active base die.
    Type: Application
    Filed: March 23, 2022
    Publication date: September 28, 2023
    Applicant: Intel Corporation
    Inventors: Mark C. Davis, Hong Jiang, Satish Damaraju
  • Publication number: 20220107806
    Abstract: A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.
    Type: Application
    Filed: August 30, 2021
    Publication date: April 7, 2022
    Inventors: Vinodh Gopal, James D. Guilford, Gilbert M. Wolrich, Wajdi K. Feghali, Erdinc Ozturk, Martin G. Dixon, Sean P. Mirkes, Bret L. Toll, Maxim Loktyukhin, Mark C. Davis, Alexandre J. Farcy
  • Patent number: 11106461
    Abstract: A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: August 31, 2021
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, James D. Guilford, Gilbert M. Wolrich, Wajdi K. Feghali, Erdinc Ozturk, Martin G. Dixon, Sean P. Mirkes, Bret L. Toll, Maxim Loktyukhin, Mark C. Davis, Alexandre J. Farcy
  • Patent number: 10649774
    Abstract: A method in one aspect may include receiving a multiply instruction. The multiply instruction may indicate a first source operand and a second source operand. A product of the first and second source operands may be stored in one or more destination operands indicated by the multiply instruction. Execution of the multiply instruction may complete without writing a carry flag. Other methods are also disclosed, as are apparatus, systems, and instructions on machine-readable medium.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: May 12, 2020
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, James D. Guilford, Wajdi K. Feghali, Erdinc Ozturk, Gilbert M. Wolrich, Martin G. Dixon, Mark C. Davis, Sean P. Mirkes, Alexandre J. Farcy, Bret L. Toll, Maxim Loktyukhin
  • Patent number: 10152452
    Abstract: Techniques to suppress redundant reads to register addresses and to replicate read data are disclosed. The redundant reads are suppressed when multiple source operands specify the same register address to read. Additionally, the read data is replicated to a data stream or data location corresponding to the source operands where the data read was suppressed.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: December 11, 2018
    Assignee: INTEL CORPORATION
    Inventors: Supratim Pal, Subramaniam Maiyuran, Mark C. Davis
  • Publication number: 20180321940
    Abstract: A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.
    Type: Application
    Filed: March 29, 2018
    Publication date: November 8, 2018
    Applicant: lntel Corporation
    Inventors: Vinodh Gopal, James D. Guilford, Gilbert M. Wolrich, Wajdi K. Feghali, Erdinc Ozturk, Martin G. Dixon, Sean P. Mirkes, Bret L. Toll, Maxim Loktyukhin, Mark C. Davis, Alexandre J. Farcy
  • Patent number: 9990201
    Abstract: A method in one aspect may include receiving a multiply instruction. The multiply instruction may indicate a first source operand and a second source operand. A product of the first and second source operands may be stored in one or more destination operands indicated by the multiply instruction. Execution of the multiply instruction may complete without writing a carry flag. Other methods are also disclosed, as are apparatus, systems, and instructions on machine-readable medium.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: June 5, 2018
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, James D. Guilford, Wajdi K. Feghali, Erdine Ozturk, Gilbert M. Wolrich, Martin G. Dixon, Mark C. Davis, Sean P. Mirkes, Alexandre Farcy, Bret L. Toll, Maxim Loktyukhin
  • Publication number: 20180136936
    Abstract: A method in one aspect may include receiving a multiply instruction. The multiply instruction may indicate a first source operand and a second source operand. A product of the first and second source operands may be stored in one or more destination operands indicated by the multiply instruction. Execution of the multiply instruction may complete without writing a carry flag. Other methods are also disclosed, as are apparatus, systems, and instructions on machine-readable medium.
    Type: Application
    Filed: December 27, 2017
    Publication date: May 17, 2018
    Applicant: Intel Corporation
    Inventors: Vinodh Gopal, James D. Guilford, Wajdi K. Feghali, Erdinc Ozturk, Gilbert M. Wolrich, Martin G. Dixon, Mark C. Davis, Sean P. Mirkes, Alexandre J. Farcy, Bret L. Toll, Maxim Loktyukhin
  • Patent number: 9940131
    Abstract: A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: April 10, 2018
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, James D Guilford, Gilbert M Wolrich, Wajdi K Feghali, Erdinc Ozturk, Martin G Dixon, Sean Mirkes, Bret L Toll, Maxim Loktyukhin, Mark C Davis, Alexandre J Farcy
  • Patent number: 9940130
    Abstract: A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: April 10, 2018
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, James D Guilford, Gilbert M Wolrich, Wajdi K Feghali, Erdinc Ozturk, Martin G Dixon, Sean Mirkes, Bret L Toll, Maxim Loktyukhin, Mark C Davis, Alexandre J Farcy
  • Patent number: 9916160
    Abstract: A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: March 13, 2018
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, James D. Guilford, Gilbert M. Wolrich, Wajdi K Feghali, Erdinc Ozturk, Martin G Dixon, Sean Mirkes, Bret L Toll, Maxim Loktyukhin, Mark C Davis, Alexandre J Farcy
  • Patent number: 9619282
    Abstract: One aspect provides a method including: identifying a task to be scheduled for execution on an information handling device having two or more cores of different size; determining an appropriate scheduling of the task for execution on the two or more of cores of different size, wherein the appropriate scheduling of the task is determined via a core signature for the task; directing the task to an appropriate core for execution based on the appropriate scheduling determined; and executing the task on the appropriate core. Other aspects are described and claimed.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: April 11, 2017
    Assignee: Lenovo (Singapore) Pte. Ltd.
    Inventors: Mark C. Davis, Daryl C. Cromer, Howard J. Locker, Scott E. Kelso
  • Patent number: 9594711
    Abstract: Systems and methods described herein provide for a process for managing continuity of experience between operation of a hybrid computer system in the connected state and the slate component independently in the disconnected state. Embodiments further provide for the continuity of experience for devices operating under multiple processors or multiple platforms. According to embodiments, one or more states and conditions of the connected hybrid computer system may be synchronized with the slate component when the slate component is disconnected from the hybrid computer system. Alternatively, embodiments provide for the synchronization of one or more states and conditions of the independent slate component with the hybrid computer system responsive to connecting the slate component to the hybrid computer system. Non-limiting examples of states and conditions according to embodiments are web pages, applications, documents, lists of recently opened files and web pages, and web browser active tabs.
    Type: Grant
    Filed: December 24, 2010
    Date of Patent: March 14, 2017
    Assignee: Lenovo (Singapore) Pte. Ltd.
    Inventors: Jennifer G. Zawacki, Steven R. Perrin, Mark C. Davis, Scott E. Kelso, Matthew Roper, Wang Zhe Peng, Wang Kai, Rong Yang, Wang Wen
  • Publication number: 20160350112
    Abstract: Techniques to suppress redundant reads to register addresses and to replicate read data are disclosed. The redundant reads are suppressed when multiple source operands specify the same register address to read. Additionally, the read data is replicated to a data stream or data location corresponding to the source operands where the data read was suppressed.
    Type: Application
    Filed: May 29, 2015
    Publication date: December 1, 2016
    Applicant: Intel Corporation
    Inventors: SUPRATIM PAL, SUBRAMANIAM MAIYURAN, MARK C. DAVIS
  • Patent number: 9507558
    Abstract: Embodiments operating shared peripherals in a hybrid computing system are described. Embodiments control one or more shared peripheral devices variously between a primary system and a secondary system via one or more communication links, where the secondary system is detachable from the primary system and operates as an independent computing device in the disconnected state, while operating as a display device in the connected state.
    Type: Grant
    Filed: December 24, 2010
    Date of Patent: November 29, 2016
    Assignee: Lenovo (Singapore) Pte. Ltd.
    Inventors: Mark C. Davis, Chen Hao, Jin Yuru, Chen Xingwen, Michael T. Vanover
  • Patent number: 9164762
    Abstract: A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: October 20, 2015
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, James D. Gulilford, Gilbert M. Wolrich, Waidi K. Feghali, Erdinc Ozturk, Martin G. Dixon, Sean P. Mirkes, Bret L. Toll, Maxim Loktyukhin, Mark C. Davis, Alexandre J. Farcy
  • Patent number: 9002925
    Abstract: Systems and methods described herein provide for communication between a base component and a slate component of a hybrid computing system. The hybrid computing system is in a connected state when the base component and slate component are connected. Embodiments provide that the base component may control the slate component when the hybrid computing system is in a connected state. In addition, embodiments provide that a server module running on the display component and a client module running on the base component facilitate communication between the hybrid computing system components. Furthermore, systems and methods described herein provide that the base component may control hardware devices, peripheral devices, or software applications of the display component through communications between the server module and client module.
    Type: Grant
    Filed: December 24, 2010
    Date of Patent: April 7, 2015
    Assignee: Lenovo (Singapore) Pte. Ltd.
    Inventors: Matthew Roper, Steven R. Perrin, Scott E. Kelso, Mark C. Davis, Li Bin, Wang Sheng