Abstract: A Scalable and Unified Compute System performs scalable, repairable general purpose and graphics shading operations, memory load/store operations and texture filtering. A Scalable and Unified Compute. Unit Module comprises a shader pipe array, a texture mapping unit, and a level one texture cache system. It accepts ALU instructions, input/output instructions, and texture or memory requests for a specified set of pixels, vertices, primitives, surfaces, or general compute work items from a shader program and performs associated operations to compute the programmed output data. The texture mapping unit accepts source data addresses and instruction constants in order to fetch, format, and perform instructed filtering interpolations to generate formatted results based on the specific corresponding data stored in a level one texture cache system. The texture mapping unit consists of an address generating system, a pre-formatter module, interpolator module, accumulator module and a format module.

Abstract: A shader pipe texture filter utilizes a level one cache system as a primary method of storage but with the ability to have the level one cache system read and write to a level two cache system when necessary. The level one cache system communicates with the level two cache system via a wide channel memory bus. In addition, the level one cache system can be configured to support dual shader pipe texture filters while maintaining access to the level two cache system. A method utilizing a level one cache system as a primary method of storage with the ability to have the level one cache system read and write a level two cache system when necessary is also presented. In addition, level one cache systems can allocate a defined area of memory to be sharable amongst other resources.

Abstract: A shader pipe texture filter utilizes a level one cache system as a primary method of storage but with the ability to have the level one cache system read and write to a level two cache system when necessary. The level one cache system communicates with the level two cache system via a wide channel memory bus. In addition, the level one cache system can be configured to support dual shader pipe texture filters while maintaining access to the level two cache system. A method utilizing a level one cache system as a primary method of storage with the ability to have the level one cache system read and write a level two cache system when necessary is also presented. In addition, level one cache systems can allocate a defined area of memory to be sharable amongst other resources.

Abstract: Each row of a row based shader engine comprises a shader pipe array, a texture filter, and a level one texture cache system. The shader pipe array accepts texture requests for a specified pixel from a resource and performs associated rendering calculations, outputting texel data. The texture mapping unit receives texel data from a level one cache system and through formatting and bilinear filtering interpolations, generates a formatted bilinear result based on a specific pixel's corresponding four texels. Utilizing multiple rows of a row based shader engine within the shader engine allows for the parallel processing of multiple simultaneous resource requests. A method for texture filtering utilizing a row based shader engine is also presented.

Abstract: Apparatus and systems utilizing multiple shader engines where each shader engine comprises multiple rows of shader engine filters combined with level one and level two cache systems. Each unified shader engine filter comprises a shader pipe array, and a texture mapping unit with access to a level one cache system and a level two cache. The shader pipe array accepts texture requests for a specified pixel from a resource and performs associated rendering calculations, outputting texel data. The texture mapping unit retrieves texel data stored in a level one cache system, with the ability to read and write to and from a level two cache system, and through formatting and bilinear filtering interpolations generates a formatted bilinear result based on the specific pixel's neighboring texels. Utilizing multiple rows of shader engine filters within a shader engine allows for the parallel processing of multiple simultaneous resource requests.

Abstract: A Scalable and Unified Compute System performs scalable, repairable general purpose and graphics shading operations, memory load/store operations and texture filtering. A Scalable and Unified Compute Unit Module comprises a shader pipe array, a texture mapping unit, and a level one texture cache system. The Scalable and Unified Compute Unit Module accepts ALU instructions, input/output instructions, and texture or memory requests for a specified set of pixels, vertices, primitives, surfaces, or general compute work items from a shader program and performs associated operations to compute the programmed output data. The texture mapping unit accepts source data addresses and instruction constants in order to fetch, format, and perform instructed filtering interpolations to generate formatted results based on the specific corresponding data stored in a level one texture cache system.

Abstract: The optimized primitive filler is used in a computer system, such as a computer system that displays graphic images. A first step of the method it is determined if a primitive is totally outside a predetermined screen region or at least partially within the predetermined screen region. The primitive is then discarded if the primitive is totally outside the screen region. If the primitive is not totally outside the screen region, at least a portion of the primitive is identified that lies within the screen region. Then only those pixels in the portion of the primitive that is inside the screen region are filled. These steps are executed for each primitive of a plurality of primitives that forms a scene of which the screen region is the portion that the computer system displays. No pixels are filled in primitives which are totally outside the screen region, and no pixels are filled in portions of primitives that are outside the screen region.

Abstract: A computer system includes a computer system having a system memory and a bridging device coupled to the system memory, the bridging device including a memory controller. The computer system also includes a graphics processor unit (GPU) coupled to one port of the bridging device and a central processing unit (CPU) coupled to another port of the bridging device. The GPU and the CPU access the system memory via the memory controller.

Abstract: A system for traversing and rendering a graphic primitive, comprising a setup engine that outputs representative values of a graphic primitive; and a raster engine that receives the representative values of the graphic primitive and forms therefrom representative pixels, the raster engine having at least a scan module that scans only pixels within the graphic primitive and assigns data values to each of the pixels and a look-ahead module that identifies pixels that are inside of the primitive.

Abstract: A method and apparatus for processing portions of primitives that are being rendered is presented. Primitives that are received are divided into portions that correspond to pixel blocks of the frame. The frame includes a plurality of pixel blocks where each of the pixel blocks includes a plurality of pixels that are included in the frame. Thus, the pixel blocks divide the frame into a number of smaller blocks. A representative Z value for each portion of the primitive is determined, and the representative Z value for the portion of the primitive is compared with a representative buffered Z, which may be the representative buffer Z value for the pixel block to which the portion corresponds. If the representative Z value for the portion compares favorably with the representative buffered Z value such that the portion is determined to lie completely behind the information currently stored for that pixel block, the portion is discarded.

Abstract: A method and apparatus for multipass pixel processing is presented. A command stream that includes a plurality of drawing commands is received where multipass drawing commands included in the stream include a number of sets of state information and one or more graphics primitives. For a multipass pixel processing operation, the graphics pipeline that performs the pixel processing is first configured using a first set of state information included in the sets of state information for the multipass operation. Once the graphics pipeline has been configured, at least a portion of the processing to be performed for the drawing command is performed using the graphics pipeline as configured by this first set of state information. The resultant data produced through this processing is stored as intermediate data. This may be referred to as the first pass in the multipass operation. The graphics pipeline is then reconfigured using a subsequent set of state information corresponding to the multipass drawing command.

Abstract: A multi-pass pixel processing circuit and method that allows a single set of texturing circuitry to be used for performing texture mapping operations that map multiple texture maps to a video graphics primitive is presented. The multi-pass pixel processing circuit includes a raster engine that is operably coupled to receive primitive parameters corresponding to video graphics primitives. For each portion of a selected primitive, the raster engine performs a first pass of texture map coordinate generation. During the first pass, the raster engine generates a first set of texture map coordinates corresponding to a first texture map for each pixel in the portion of the selected video graphics primitive. A coordinate combination block that is operably coupled to the raster engine provides the first set of texture map coordinates for each pixel to a memory that stores the first texture map to retrieve texture data corresponding to the first texture map for each pixel.

Abstract: A method and apparatus for determining and utilizing Z values of fragments in an anti-aliasing video graphics system is described. This method and apparatus are accomplished by sampling the fragment to produce a plurality of samples where a valid sample indicate coverage of a pixel by the fragment at a portion of the pixel corresponding to the valid sample. The Z value of a front-most valid sample of the plurality of samples is then determined. This Z value is preferably determined by determining the Z value at a reference point within the pixel and then ranking the various samples based on their positions and the slopes of the Z value in the horizontal and vertical directions with respect to the reference point. The highest ranked sample that is a valid sample is then selected, and the Z value for that sample is calculated based on the Z value at the reference point, the position of the selected sample with respect to the reference point, and the slopes.

Abstract: A method and apparatus for reducing memory bandwidth usage in video graphics texturing operations that utilizes caching of compressed textures is presented. Texture information for texturing operations is stored in a memory structure in a compressed format. When texture information is needed for a texturing operation, a local cache is first examined to determine if the texture information required for the texturing operation is present within the cache. If it is not, the texture information is retrieved from the memory in a compressed format and stored in the cache in the compressed format. The compressed texture information is then retrieved from the cache each time it is required for a texturing operation and decompressed prior to use in such texturing operations.

Abstract: A parallel vector generator in which an Nx .times.Ny array of processors, each assigned to one particular pixel of each Nx .times.Ny block of contiguous pixels, operate concurrently to generate a pixel image of a line. Each processor of the array executes a version of the Bresenham line-drawing procedure that is modified so that iterations for pixels over which the processor has no control is eliminated. The processors are capable of processing lines having subpixel endpoints while using only integer arithmetic. Each processor contains a pair of parallel vector generators that are used to generate the endpoints of a triangle along each scan line.