Patents by Inventor Mark C. Lamorey
Mark C. Lamorey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11049819Abstract: Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.Type: GrantFiled: November 15, 2019Date of Patent: June 29, 2021Assignee: International Business Machines CorporationInventors: Mark C. Lamorey, Janak G. Patel, Peter Slota, Jr., David B. Stone
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Patent number: 10685919Abstract: A laminate structure includes a conductive layer and a dielectric layer in contact with the conductive layer, the dielectric layer comprises a selectively patterned high-modulus dielectric material that balances a differential stress between the conductive layer and the dielectric layer to mechanically stiffen the laminate structure and reduce warpage.Type: GrantFiled: February 7, 2017Date of Patent: June 16, 2020Assignee: International Business Machines CorporationInventors: Mark C. Lamorey, Shidong Li, Janak G. Patel, Douglas O. Powell, David J. Russell, Peter Slota, Jr., David B. Stone
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Publication number: 20200083177Abstract: Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.Type: ApplicationFiled: November 15, 2019Publication date: March 12, 2020Inventors: Mark C. Lamorey, Janak G. Patel, Peter Slota, Jr., David B. Stone
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Patent number: 10553544Abstract: Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.Type: GrantFiled: October 27, 2017Date of Patent: February 4, 2020Assignee: International Business Machines CorporationInventors: Mark C. Lamorey, Janak G. Patel, Peter Slota, Jr., David B. Stone
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Patent number: 10032560Abstract: A method of manufacturing a variable capacitor includes forming a capacitor conductor. The method also includes forming a phase change material adjacent the capacitor conductor. The method further includes forming a first contact on the capacitor conductor. The method additionally includes forming a second contact and a third contact on the phase change material.Type: GrantFiled: November 13, 2015Date of Patent: July 24, 2018Assignee: Western Digital Technologies, Inc.Inventor: Mark C. Lamorey
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Patent number: 9935058Abstract: Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.Type: GrantFiled: November 21, 2016Date of Patent: April 3, 2018Assignee: International Business Machines CorporationInventors: Mark C. Lamorey, Janak G. Patel, Peter Slota, Jr., David B. Stone
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Publication number: 20180068957Abstract: Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.Type: ApplicationFiled: October 27, 2017Publication date: March 8, 2018Inventors: Mark C. Lamorey, Janak G. Patel, Peter Slota, JR., David B. Stone
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Publication number: 20170148749Abstract: A laminate structure includes a conductive layer and a dielectric layer in contact with the conductive layer, the dielectric layer comprises a selectively patterned high-modulus dielectric material that balances a differential stress between the conductive layer and the dielectric layer to mechanically stiffen the laminate structure and reduce warpage.Type: ApplicationFiled: February 7, 2017Publication date: May 25, 2017Inventors: Mark C. Lamorey, Shidong Li, Janak G. Patel, Douglas O. Powell, David J. Russell, Peter Slota, JR., David B. Stone
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Publication number: 20170125358Abstract: Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.Type: ApplicationFiled: November 21, 2016Publication date: May 4, 2017Inventors: Mark C. Lamorey, Janak G. Patel, Peter Slota, JR., David B. Stone
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Patent number: 9613915Abstract: A laminate structure includes a conductive layer and a dielectric layer in contact with the conductive layer, the dielectric layer comprises a selectively patterned high-modulus dielectric material that balances a differential stress between the conductive layer and the dielectric layer to mechanically stiffen the laminate structure and reduce warpage.Type: GrantFiled: December 2, 2014Date of Patent: April 4, 2017Assignee: International Business Machines CorporationInventors: Mark C. Lamorey, Shidong Li, Janak G. Patel, Douglas O. Powell, David J. Russell, Peter Slota, Jr., David B. Stone
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Patent number: 9543255Abstract: A laminate structure includes a conductive layer and a dielectric layer in contact with the conductive layer, the dielectric layer comprises a selectively patterned high-modulus dielectric material that balances a differential stress between the conductive layer and the dielectric layer to mechanically stiffen the laminate structure and reduce warpage.Type: GrantFiled: February 15, 2016Date of Patent: January 10, 2017Assignee: International Business Machines CorporationInventors: Mark C. Lamorey, Shidong Li, Janak G. Patel, Douglas O. Powell, David J. Russell, Peter Slota, Jr., David B. Stone
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Patent number: 9543254Abstract: A corner crackstop is formed in each of the four corners of an integrated circuit (IC) chip, in which the corner crackstop differs structurally from a portion of the crackstop disposed along the sides of the IC chip. Each corner crackstop includes a plurality of layers, formed on a top surface of a silicon layer of the IC chip, within a perimeter boundary region that comprises a triangular area, in which a right angle is disposed on a bisector of the corner, equilateral sides of the triangle are parallel to sides of the IC chip, and the right angle is proximate to the corner relative to a hypotenuse of the triangle. The plurality of layers of the corner crackstop include crackstop elements, each comprising a metal cap centered over a via bar, in which the plurality of layers of the corner crackstop is chamfered to deflect crack ingress forces by each corner crackstop.Type: GrantFiled: May 13, 2015Date of Patent: January 10, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Mark C. Lamorey, David B. Stone
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Patent number: 9531209Abstract: Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.Type: GrantFiled: August 10, 2015Date of Patent: December 27, 2016Assignee: International Business Machines CorporationInventors: Mark C. Lamorey, Janak G. Patel, Peter Slota, Jr., David B. Stone
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Publication number: 20160155708Abstract: A laminate structure includes a conductive layer and a dielectric layer in contact with the conductive layer, the dielectric layer comprises a selectively patterned high-modulus dielectric material that balances a differential stress between the conductive layer and the dielectric layer to mechanically stiffen the laminate structure and reduce warpage.Type: ApplicationFiled: December 2, 2014Publication date: June 2, 2016Inventors: Mark C. Lamorey, Shidong Li, Janak G. Patel, Douglas O. Powell, David J. Russell, Peter Slota, JR., David B. Stone
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Publication number: 20160157357Abstract: A laminate structure includes a conductive layer and a dielectric layer in contact with the conductive layer, the dielectric layer comprises a selectively patterned high-modulus dielectric material that balances a differential stress between the conductive layer and the dielectric layer to mechanically stiffen the laminate structure and reduce warpage.Type: ApplicationFiled: February 15, 2016Publication date: June 2, 2016Inventors: Mark C. Lamorey, Shidong Li, Janak G. Patel, Douglas O. Powell, David J. Russell, Peter Slota, JR., David B. Stone
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Publication number: 20160071653Abstract: A method of manufacturing a variable capacitor includes forming a capacitor conductor. The method also includes forming a phase change material adjacent the capacitor conductor. The method further includes forming a first contact on the capacitor conductor. The method additionally includes forming a second contact and a third contact on the phase change material.Type: ApplicationFiled: November 13, 2015Publication date: March 10, 2016Inventor: Mark C. LAMOREY
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Patent number: 9252101Abstract: Packages for a three-dimensional die stack, methods for fabricating a package for a three-dimensional die stack, and methods for distributing power in a package for a three-dimensional die stack. The package may include a first lid, a second lid, a die stack located between the first lid and the second lid, a first thermal interface material layer between the first lid and a first die of the die stack, and a second thermal interface material layer between the second lid and the second die of the die stack. The second thermal interface material layer is comprised of a thermal interface material having a high electrical conductivity and a high thermal conductivity.Type: GrantFiled: April 2, 2015Date of Patent: February 2, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mark C. Lamorey, Janak G. Patel, Peter Slota, Jr., David B. Stone
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Patent number: 9253822Abstract: A method of manufacturing a variable capacitor includes forming a capacitor conductor. The method also includes forming a phase change material adjacent the capacitor conductor. The method further includes forming a first contact on the capacitor conductor. The method additionally includes forming a second contact and a third contact on the phase change material.Type: GrantFiled: June 25, 2013Date of Patent: February 2, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Mark C. Lamorey
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Patent number: 9209141Abstract: Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.Type: GrantFiled: February 26, 2014Date of Patent: December 8, 2015Assignee: International Business Machines CorporationInventors: Mark C. Lamorey, Janak G. Patel, Peter Slota, Jr., David B. Stone
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Publication number: 20150349565Abstract: Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.Type: ApplicationFiled: August 10, 2015Publication date: December 3, 2015Inventors: Mark C. Lamorey, Janak G. Patel, Peter Slota, JR., David B. Stone