Patents by Inventor Mark C. Phillips

Mark C. Phillips has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11925631
    Abstract: The present disclosure relates generally to certain 6-azabenzimidazole compounds, pharmaceutical compositions comprising said compounds, and methods of making and using said compounds and pharmaceutical compositions. The compounds and compositions disclosed herein may be used for the treatment or prevention of diseases, disorders, or infections modifiable by hematopoietic progenitor kinase 1 (HPK1) inhibitors, such as HBV, HIV, cancer, and/or a hyper-proliferative disease.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: March 12, 2024
    Assignee: Gilead Sciences, Inc.
    Inventors: Gayatri Balan, Mark J. Bartlett, Jayaraman Chandrasekhar, Julian A. Codelli, John H. Conway, Jennifer L. Cosman, Rao V. Kalla, Musong Kim, Seung H. Lee, Jennifer R. Lo, Jennifer A. Loyer-Drew, Scott A. Mitchell, Thao D. Perry, Gary B. Phillips, Patrick J. Salvo, Joshua J. Van Veldhuizen, Suet C. Yeung, Jeff Zablocki
  • Publication number: 20230209800
    Abstract: Stitched dies having a cooling structure are described. For example, an integrated circuit structure includes a first die including a first device layer and a first plurality of metallization layers over the first device layer. The integrated circuit structure also includes a second die including a second device layer and a second plurality of metallization layers over the second device layer, the second die separated from the second die by a scribe region. A common conductive interconnection is coupling the first die and the second die at a first side of the first and second dies. A plurality of microfluidic channels is coupled to the first side of the first and second dies.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 29, 2023
    Inventors: Abhishek Anil SHARMA, Wilfred GOMES, Christopher M. PELTO, Mark C. PHILLIPS, Swaminathan SIVAKUMAR
  • Publication number: 20230207445
    Abstract: Stitched dies having high bandwidth and capacity are described. For example, an integrated circuit structure includes a first die including a first device layer and a first plurality of metallization layers over the first device layer, wherein the first device layer is a logic device layer. The integrated circuit structure also includes a second die including a second device layer and a second plurality of metallization layers over the second device layer, the second die separated from the first die by a scribe region. The second device layer is a transistor device layer, and the second plurality of metallization layers includes a layer of capacitor structures between an upper metallization layer portion and a lower metallization layer portion. A common conductive interconnection is coupling the first die and the second die at a first side of the first and second dies.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 29, 2023
    Inventors: Abhishek Anil SHARMA, Christopher M. PELTO, Wilfred GOMES, Mark C. PHILLIPS, Swaminathan SIVAKUMAR, Shem O. OGADHOH
  • Publication number: 20230207565
    Abstract: Stitched dies having backside power delivery are described are described. For example, an integrated circuit structure includes a first die including a first device layer and a first plurality of metallization layers over the first device layer. The integrated circuit structure also includes a second die including a second device layer and a second plurality of metallization layers over the second device layer, the second die separated from the second die by a scribe region. A signal line is coupling the first die and the second die at a first side of the first and second dies. A backside power rail is coupling the first die and the second die at a second side of the first and second dies, the second side opposite the first side.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 29, 2023
    Inventors: Abhishek Anil SHARMA, Wilfred GOMES, Swaminathan SIVAKUMAR, Mark C. PHILLIPS, Christopher M. PELTO
  • Patent number: 11581162
    Abstract: Lithographic apparatuses suitable for complementary e-beam lithography (CEBL) are described. In an example, a method of forming a pattern for a semiconductor structure includes forming a pattern of parallel lines above a substrate. The method also includes aligning the substrate in an e-beam tool to provide the pattern of parallel lines parallel with a scan direction of the e-beam tool. The e-beam tool includes a column having a blanker aperture array (BAA) with a staggered pair of columns of openings along an array direction orthogonal to the scan direction. The method also includes forming a pattern of cuts or vias in or above the pattern of parallel lines to provide line breaks for the pattern of parallel lines by scanning the substrate along the scan direction. A cumulative current through the column has a non-zero and substantially uniform cumulative current value throughout the scanning.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: February 14, 2023
    Assignee: Intel Corporation
    Inventors: Shakul Tandon, Mark C. Phillips, Shem O. Ogadhoh, John A. Swanson
  • Publication number: 20210358713
    Abstract: Lithographic apparatuses suitable for complementary e-beam lithography (CEBL) are described. In an example, a method of forming a pattern for a semiconductor structure includes forming a pattern of parallel lines above a substrate. The method also includes aligning the substrate in an e-beam tool to provide the pattern of parallel lines parallel with a scan direction of the e-beam tool. The e-beam tool includes a column having a blanker aperture array (BAA) with a staggered pair of columns of openings along an array direction orthogonal to the scan direction. The method also includes forming a pattern of cuts or vias in or above the pattern of parallel lines to provide line breaks for the pattern of parallel lines by scanning the substrate along the scan direction. A cumulative current through the column has a non-zero and substantially uniform cumulative current value throughout the scanning.
    Type: Application
    Filed: July 29, 2021
    Publication date: November 18, 2021
    Inventors: Shakul TANDON, Mark C. PHILLIPS, Shem O. OGADHOH, John A. SWANSON
  • Patent number: 11107658
    Abstract: Lithographic apparatuses suitable for complementary e-beam lithography (CEBL) are described. In an example, a method of forming a pattern for a semiconductor structure includes forming a pattern of parallel lines above a substrate. The method also includes aligning the substrate in an e-beam tool to provide the pattern of parallel lines parallel with a scan direction of the e-beam tool. The e-beam tool includes a column having a blanker aperture array (BAA) with a staggered pair of columns of openings along an array direction orthogonal to the scan direction. The method also includes forming a pattern of cuts or vias in or above the pattern of parallel lines to provide line breaks for the pattern of parallel lines by scanning the substrate along the scan direction. A cumulative current through the column has a non-zero and substantially uniform cumulative current value throughout the scanning.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: August 31, 2021
    Assignee: Intel Corporation
    Inventors: Shakul Tandon, Mark C. Phillips, Shem O. Ogadhoh, John A. Swanson
  • Patent number: 10948408
    Abstract: A toroidal optical device can include a ring mirror defining a toroidal optical cavity symmetric about an axis and an optical coupler situated inside the toroidal optical cavity. The optical coupler can be situated to direct an input light first received from outside the toroidal optical cavity propagating inside the toroidal optical cavity, to multiply reflect from the ring mirror inside the toroidal optical cavity. A method includes producing one or more additional ring mirrors defining a toroidal optical cavity symmetric about a sagittal axis using a first ring mirror as a master form, and affixing an optical coupler inside the optical cavity to at least one of the one or more additional ring mirrors.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: March 16, 2021
    Assignee: Battelle Memorial Institute
    Inventors: Bruce E. Bernacki, Mark C. Phillips
  • Publication number: 20200408679
    Abstract: A toroidal optical device can include a ring mirror defining a toroidal optical cavity symmetric about an axis and an optical coupler situated inside the toroidal optical cavity. The optical coupler can be situated to direct an input light first received from outside the toroidal optical cavity propagating inside the toroidal optical cavity, to multiply reflect from the ring mirror inside the toroidal optical cavity. A method includes producing one or more additional ring mirrors defining a toroidal optical cavity symmetric about a sagittal axis using a first ring mirror as a master form, and affixing an optical coupler inside the optical cavity to at least one of the one or more additional ring mirrors.
    Type: Application
    Filed: June 25, 2019
    Publication date: December 31, 2020
    Applicant: Battelle Memorial Institute
    Inventors: Bruce E. Bernacki, Mark C. Phillips
  • Patent number: 10578970
    Abstract: Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a blanker aperture array (BAA) for an e-beam tool includes a first column of openings along a first direction. The BAA also includes a second column of openings along the first direction and staggered from the first column of openings. The first and second columns of openings together form an array having a pitch in the first direction. A scan direction of the BAA is along a second direction, orthogonal to the first direction. The pitch of the array corresponds to half of a minimal pitch layout of a target pattern of lines for orientation parallel with the second direction.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: March 3, 2020
    Assignee: Intel Corporation
    Inventors: Yan A. Borodovsky, Donald W. Nelson, Mark C. Phillips
  • Patent number: 10395883
    Abstract: Lithographic apparatuses suitable for complementary e-beam lithography (CEBL) are described. In an example, a blanker aperture array (BAA) for an e-beam tool includes a first column of openings along a first direction and having a pitch. Each opening of the first column of openings has a dimension in the first direction. The BAA also includes a second column of openings along the first direction and staggered from the first column of openings. The second column of openings has the pitch. Each opening of the second column of openings has the dimension in the first direction. A scan direction of the BAA is along a second direction orthogonal to the first direction. The openings of the first column of openings overlap with the openings of the second column of openings by at least 5% but less than 50% of the dimension in the first direction when scanned along the second direction.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: August 27, 2019
    Assignee: Intel Corporation
    Inventors: Shakul Tandon, Mark C. Phillips, Gabriele Canzi
  • Patent number: 10386722
    Abstract: Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a blanker aperture array (BAA) for an e-beam tool includes a first column of openings along a first direction and having a pitch. The BAA also includes a second column of openings along the first direction and staggered from the first column of openings. The second column of openings has the pitch. A scan direction of the BAA is along a second direction, orthogonal to the first direction.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: August 20, 2019
    Assignee: Intel Corporation
    Inventors: Yan A. Borodovsky, Donald W. Nelson, Mark C. Phillips
  • Publication number: 20190164723
    Abstract: Lithographic apparatuses suitable for complementary e-beam lithography (CEBL) are described. In an example, a method of forming a pattern for a semiconductor structure includes forming a pattern of parallel lines above a substrate. The method also includes aligning the substrate in an e-beam tool to provide the pattern of parallel lines parallel with a scan direction of the e-beam tool. The e-beam tool includes a column having a blanker aperture array (BAA) with a staggered pair of columns of openings along an array direction orthogonal to the scan direction. The method also includes forming a pattern of cuts or vias in or above the pattern of parallel lines to provide line breaks for the pattern of parallel lines by scanning the substrate along the scan direction. A cumulative current through the column has a non-zero and substantially uniform cumulative current value throughout the scanning.
    Type: Application
    Filed: September 30, 2016
    Publication date: May 30, 2019
    Inventors: Shakul TANDON, Mark C. PHILLIPS, Shem O. OGADHOH, John A. SWANSON
  • Publication number: 20190155160
    Abstract: Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a blanker aperture array (BAA) for an e-beam tool includes a first column of openings along a first direction. The BAA also includes a second column of openings along the first direction and staggered from the first column of openings. The first and second columns of openings together form an array having a pitch in the first direction. A scan direction of the BAA is along a second direction, orthogonal to the first direction. The pitch of the array corresponds to half of a minimal pitch layout of a target pattern of lines for orientation parallel with the second direction.
    Type: Application
    Filed: January 18, 2019
    Publication date: May 23, 2019
    Inventors: Yan A. BORODOVSKY, Donald W. NELSON, Mark C. PHILLIPS
  • Patent number: 10290528
    Abstract: Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a method of real-time alignment of a wafer situated on a stage of an e-beam tool involves collecting backscattered electrons from an underlying patterned feature of the wafer while an e-beam column of the e-beam tool writes during scanning of the stage. The collecting is performed by an electron detector placed at the e-beam column bottom. The method also involves performing linear corrections of an alignment of the stage relative to the e-beam column based on the collecting.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: May 14, 2019
    Assignee: Intel Corporation
    Inventors: Yan A. Borodovsky, Donald W. Nelson, Mark C. Phillips
  • Patent number: 10216087
    Abstract: Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a blanker aperture array (BAA) for an e-beam tool includes a first column of openings along a first direction. The BAA also includes a second column of openings along the first direction and staggered from the first column of openings. The first and second columns of openings together form an array having a pitch in the first direction. A scan direction of the BAA is along a second direction, orthogonal to the first direction. The pitch of the array corresponds to half of a minimal pitch layout of a target pattern of lines for orientation parallel with the second direction.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: February 26, 2019
    Assignee: Intel Corporation
    Inventors: Yan A. Borodovsky, Donald W. Nelson, Mark C. Phillips
  • Publication number: 20190013175
    Abstract: Lithographic apparatuses suitable for complementary e-beam lithography (CEBL) are described. In an example, a blanker aperture array (BAA) for an e-beam tool includes a first column of openings along a first direction and having a pitch. Each opening of the first column of openings has a dimension in the first direction. The BAA also includes a second column of openings along the first direction and staggered from the first column of openings. The second column of openings has the pitch. Each opening of the second column of openings has the dimension in the first direction. A scan direction of the BAA is along a second direction orthogonal to the first direction. The openings of the first column of openings overlap with the openings of the second column of openings by at least 5% but less than 50% of the dimension in the first direction when scanned along the second direction.
    Type: Application
    Filed: March 31, 2016
    Publication date: January 10, 2019
    Inventors: Shakul TANDON, Mark C. PHILLIPS, Gabriele CANZI
  • Patent number: 10067416
    Abstract: Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a blanker aperture array (BAA) for an e-beam tool is described. The BAA includes three distinct aperture arrays of different pitch.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: September 4, 2018
    Assignee: Intel Corporation
    Inventors: Yan A. Borodovsky, Donald W. Nelson, Mark C. Phillips
  • Patent number: 10014256
    Abstract: Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a layout for a metallization layer of an integrated circuit includes a first region having a plurality of unidirectional lines of a first width and a first pitch and parallel with a first direction. The layout also includes a second region having a plurality of unidirectional lines of a second width and a second pitch and parallel with the first direction, the second width and the second pitch different than the first width and the first pitch, respectively. The layout also includes a third region having a plurality of unidirectional lines of a third width and a third pitch and parallel with the first direction, the third width and the third pitch different than the first and second widths and different than the first and second pitches.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: July 3, 2018
    Assignee: Intel Corporation
    Inventors: Donald W. Nelson, Yan A. Borodovsky, Mark C. Phillips
  • Publication number: 20180143526
    Abstract: Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a blanker aperture array (BAA) for an e-beam tool is described. The BAA includes three distinct aperture arrays of different pitch.
    Type: Application
    Filed: January 17, 2018
    Publication date: May 24, 2018
    Inventors: Yan A. BORODOVSKY, Donald W. NELSON, Mark C. PHILLIPS