Abstract: A method of preparing a set of target layout data for the application of a photolithographic friendly design (LFD) analysis or other photolithographic analysis. The target layout data is revised to remove areas or features prior to performing the LFD analysis. The features removed include features that have been determined to print correctly, duplicate features and features that are not sensitive to variations in process conditions. The revised target layout is analyzed to determine if the features that remain will print correctly on a wafer.

Abstract: Aspects of the invention relate to techniques for improving speed and consistency of OPC processes based on pattern matching. Pattern matching may be performed on a layout design to determine one or more arrays in the layout design that comprise arrays of identical layout patterns of which each matches a reference pattern. The one or more arrays may then be partitioned into core portions and boundary portions. The OPC process information for the reference pattern may be applied to the core portions, while a conventional OPC process may be performed on the boundary portions and layout regions outside of the one or more arrays.

Abstract: A method of preparing a set of target layout data for the application of a photolithographic friendly design (LFD) analysis or other photolithographic analysis. The target layout data is revised to remove areas or features prior to performing the LFD analysis. The features removed include features that have been determined to print correctly, duplicate features and features that are not sensitive to variations in process conditions. The revised target layout is analyzed to determine if the features that remain will print correctly on a wafer.

Abstract: A method of preparing a set of target layout data for the application of a photolithographic friendly design (LFD) analysis or other photolithographic analysis. The target layout data is revised to remove areas or features prior to performing the LFD analysis. The features removed include features that have been determined to print correctly, duplicate features and features that are not sensitive to variations in process conditions. The revised target layout is analyzed to determine if the features that remain will print correctly on a wafer.

Abstract: Aspects of the invention relate to techniques for improving speed and consistency of OPC processes based on pattern matching. Pattern matching may be performed on a layout design to determine one or more arrays in the layout design that comprise arrays of identical layout patterns of which each matches a reference pattern. The one or more arrays may then be partitioned into core portions and boundary portions. The OPC process information for the reference pattern may be applied to the core portions, while a conventional OPC process may be performed on the boundary portions and layout regions outside of the one or more arrays.

Abstract: Aspects of the invention relate to techniques for generating and applying pattern matching hints. Pattern matching hints are determined for and stored with reference patterns. Once layout patterns that match a reference pattern are identified in a layout design through a pattern matching process, the corresponding pattern matching hints may be associated with the identified layout patterns. The association operation may comprise adjusting the identified layout patterns based on the corresponding pattern matching hints.

Abstract: Aspects of the invention relate to pattern matching of layout design data. Layout design data is searched to identify configurations of geometric elements that match a reference pattern based on an anchor edge in the reference pattern. An edge in a search window area matching the anchor edge may first be selected as anchor matching edge. A search portion of the reference pattern is then compared with the region of the search window area corresponding to the selected anchor matching edge.

Abstract: Aspects of the invention relate to pattern matching of layout design data. Layout design data is searched to identify configurations of geometric elements that match a reference pattern based on an anchor edge in the reference pattern. An edge in a search window area matching the anchor edge may first be selected as anchor matching edge. A search portion of the reference pattern is then compared with the region of the search window area corresponding to the selected anchor matching edge.

Abstract: A method of preparing a set of target layout data for the application of a photolithographic friendly design (LFD) analysis or other photolithographic analysis. The target layout data is revised to remove areas or features prior to performing the LFD analysis. The features removed include features that have been determined to print correctly, duplicate features and features that are not sensitive to variations in process conditions. The revised target layout is analyzed to determine if the features that remain will print correctly on a wafer.

Abstract: A pre-bias optical proximity correction (OPC) method allows faster convergence during OPC iterations, providing an initial set of conditions to edge fragments of a layout based on density conditions near the edge fragments.

Abstract: A method of preparing a set of target layout data for the application of a photolithographic friendly design (LFD) analysis or other photolithographic analysis. The target layout data is revised to remove areas or features prior to performing the LFD analysis. The features removed include features that have been determined to print correctly, duplicate features and features that are not sensitive to variations in process conditions. The revised target layout is analyzed to determine if the features that remain will print correctly on a wafer.

Abstract: A pre-bias optical proximity correction (OPC) method allows faster convergence during OPC iterations, providing an initial set of conditions to edge fragments of a layout based on density conditions near the edge fragments.

Abstract: A pre-bias optical proximity correction (OPC) method allows faster convergence during OPC iterations, providing an initial set of conditions to edge fragments of a layout based on density conditions near the edge fragments.

Abstract: A pre-bias optical proximity correction (OPC) method allows faster convergence during OPC iterations, providing an initial set of conditions to edge fragments of a layout based on density conditions near the edge fragments.

Abstract: A method of preparing a set of target layout data for the application of a photolithographic friendly design (LFD) analysis or other photolithographic analysis. The target layout data is revised to remove areas or features prior to performing the LFD analysis. The features removed include features that have been determined to print correctly, duplicate features and features that are not sensitive to variations in process conditions. The revised target layout is analyzed to determine if the features that remain will print correctly on a wafer.

Abstract: The invention provides a method of measuring a standard critical dimension feature and insuring that this feature is representative of cross-chip average critical dimension size in accordance with an embodiment of the invention. The method includes the steps of incorporating a cluster of CD features, determining a cross-chip average feature size, selecting the CD feature which is closest in size to the cross-chip average CD feature size as the standard feature for in-line measurement, and implementing the CD measurement of the appropriate feature on production wafers.

Abstract: The invention provides a method of measuring a standard critical dimension feature and insuring that this feature is representative of cross-chip average critical dimension size in accordance with an embodiment of the invention. The method includes the steps of incorporating a cluster of CD features, determining a cross-chip average feature size, selecting the CD feature which is closest in size to the cross-chip average CD feature size as the standard feature for in-line measurement, and implementing the CD measurement of the appropriate feature on production wafers.