Abstract: In a computer I/O system including a plurality of link-level facilities and a dynamic switch having a plurality of ports, each link-level facility being attached to an individual one of the ports, a mechanism and method for assigning a unique link level address to each of the link-level facilities. As each of the link-level facilities comes on line, it sends an acquire link address (ALA) frame and waits for a response (ACK) frame. The ALA frame may be addressed to a general to-whom-it-may-concern address and have a source address of who-am-I. Only a dynamic switch normally assigns link addresses. When receiving an ALA frame, the dynamic switch returns an ACK frame having a unique link address assigned to the sender of the ALA frame. Provision is made for determining if there is a dynamic switch present, or, if the link-level facilities are connected together by a static connection through the dynamic switch, for the link-level facility of a channel to assign the unique link addresses.

Abstract: In a computer system, a plurality of input/output processors (IOP's) are connected via an asynchronous input/output bus, called an "SPD" bus, to one side of an input/output interface controller (IOIC). The other side of the IOIC is connected to a storage controller (SC) via a synchronous bus called an "adapter" bus. The SC is connected to a common system memory and possibly also to an instruction processing unit. The IOIC comprises at least one shared DMA facility for executing DMA read/write storage operations requested by the IOP's via the SPD bus. Each shared DMA facility includes a buffer for holding control information and data to be transmitted between the SC and one of the IOP's. This enables the SPD bus to be released for utilization by otehr IOP's connected thereto during periods of "storage latency" that occur after a DMA storage operation has been initiated by one IOP.

Abstract: An input/output bus for a data processing system which has extended addressing capabilities and a variable length handshake which accommodates the difference delays associated with various sets of logic and a two part address field which allows a bus unit and channel to be identified. The various units can disconnect from the bus during internal processing to free the bus for other activity. The unit removes the busy signal prior to dropping the data lines to allow a bus arbitration sequence to occur without slowing down the bus.

Abstract: A synchronous parallel data bus particularly adapted for use in a data processing system where it is necessary to transfer data over long distances. The physical connection between communicating units includes a plurality of wires adapted to carry the parallel data signal and a wire which carries a clock signal to the remote unit. When data is transmitted from the remote unit to the base unit, the clock signal which originated at the base unit and was transmitted to the remote unit is "turned around" and transmitted back to the base unit for use in receiving the data from the remote unit.