Patents by Inventor Mark C. Spaeth

Mark C. Spaeth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method for reducing timing mismatch in sample and hold circuits using the clock
    Patent number: 6518800
    Abstract: The present invention relates to a high speed sample and hold circuit which comprises a plurality of sample and hold subcircuits coupled in parallel between an input and an output. The circuit also comprises a calibration circuit coupled to the plurality of sample and hold subcircuits. The calibration circuit is operable to establish a timing relationship between a hold signal and a clock signal for each of the plurality of sample and hold subcircuits which is generally the same. The established timing relationship reduces a timing mismatch between the plurality of sample and hold subcircuits and distortion associated therewith. The present invention also comprises a method of reducing timing mismatch in a high speed, parallel coupled sample and hold circuit.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: February 11, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: David A. Martin, Mark C. Spaeth
  • System and method for reducing timing mismatch in sample and hold circuits using an FFT and decimation
    Patent number: 6483448
    Abstract: The present invention relates to a high speed sample and hold circuit which comprises a plurality of sample and hold subcircuits coupled in parallel between an input and an output. The circuit also comprises a calibration circuit coupled to the plurality of sample and hold subcircuits. The calibration circuit is operable to modify a hold signal for one or more of the plurality of sample and hold subcircuits to thereby reduce timing mismatch between the plurality of sample and hold subcircuits and distortion associated therewith. The present invention also comprises a method of reducing timing mismatch in a high speed, parallel coupled sample and hold circuit. The method comprises detecting timing mismatch associated with a plurality of sample and hold subcircuits and modifying a hold signal for one or more of the subcircuits.
    Type: Grant
    Filed: June 22, 2001
    Date of Patent: November 19, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: David A. Martin, Mark C. Spaeth
  • System and method for reducing timing mismatch in sample and hold circuits using an FFT and subcircuit reassignment
    Patent number: 6407687
    Abstract: The present invention relates to a high speed sample and hold circuit which comprises a plurality of sample and hold subcircuits coupled in parallel between an input and an output. The circuit also comprises a calibration circuit coupled to the plurality of sample and hold subcircuits. The calibration circuit is operable to modify a hold signal for one or more of the plurality of sample and hold subcircuits to thereby reduce timing mismatch between the plurality of sample and hold subcircuits and distortion associated therewith. The present invention also comprises a method of reducing timing mismatch in a high speed, parallel coupled sample and hold circuit. The method comprises detecting timing mismatch associated with a plurality of sample and hold subcircuits and modifying a hold signal for one or more of the subcircuits.
    Type: Grant
    Filed: June 22, 2001
    Date of Patent: June 18, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: David A. Martin, Mark C. Spaeth
  • System and method for reducing timing mismatch in sample and hold circuits using an FFT and decimation
    Publication number: 20020007386
    Abstract: The present invention relates to a high speed sample and hold circuit which comprises a plurality of sample and hold subcircuits coupled in parallel between an input and an output. The circuit also comprises a calibration circuit coupled to the plurality of sample and hold subcircuits. The calibration circuit is operable to modify a hold signal for one or more of the plurality of sample and hold subcircuits to thereby reduce timing mismatch between the plurality of sample and hold subcircuits and distortion associated therewith. The present invention also comprises a method of reducing timing mismatch in a high speed, parallel coupled sample and hold circuit. The method comprises detecting timing mismatch associated with a plurality of sample and hold subcircuits and modifying a hold signal for one or more of the subcircuits.
    Type: Application
    Filed: June 22, 2001
    Publication date: January 17, 2002
    Inventors: David A. Martin, Mark C. Spaeth
  • System and method for reducing timing mismatch in sample and hold circuits using an FFT and subcircuit reassignment
    Publication number: 20020000925
    Abstract: The present invention relates to a high speed sample and hold circuit which comprises a plurality of sample and hold subcircuits coupled in parallel between an input and an output. The circuit also comprises a calibration circuit coupled to the plurality of sample and hold subcircuits. The calibration circuit is operable to modify a hold signal for one or more of the plurality of sample and hold subcircuits to thereby reduce timing mismatch between the plurality of sample and hold subcircuits and distortion associated therewith. The present invention also comprises a method of reducing timing mismatch in a high speed, parallel coupled sample and hold circuit. The method comprises detecting timing mismatch associated with a plurality of sample and hold subcircuits and modifying a hold signal for one or more of the subcircuits.
    Type: Application
    Filed: June 22, 2001
    Publication date: January 3, 2002
    Inventors: David A. Martin, Mark C. Spaeth
  • System and method for reducing timing mismatch in sample and hold circuits using the clock
    Publication number: 20010048729
    Abstract: The present invention relates to a high speed sample and hold circuit which comprises a plurality of sample and hold subcircuits coupled in parallel between an input and an output. The circuit also comprises a calibration circuit coupled to the plurality of sample and hold subcircuits. The calibration circuit is operable to establish a timing relationship between a hold signal and a clock signal for each of the plurality of sample and hold subcircuits which is generally the same. The established timing relationship reduces a timing mismatch between the plurality of sample and hold subcircuits and distortion associated therewith. The present invention also comprises a method of reducing timing mismatch in a high speed, parallel coupled sample and hold circuit.
    Type: Application
    Filed: May 25, 2001
    Publication date: December 6, 2001
    Inventors: David A. Martin, Mark C. Spaeth