Abstract: A video codec includes a stitching module configured to select stored encoded video frames that are to be composed into a concatenated frame for display. The stitching module arranges the selected encoded video frames into a specified pattern, and stitches the arranged encoded video frames together to generate a stitched encoded frame. A decoder of the video codec then decodes the stitched encoded frame to generate the frame for display.

Abstract: An integrated circuit includes a buffer circuit, a receiving circuit, and a programmable repeater circuit. The programmable repeater circuit includes a routing input and an enable input. The programmable repeater circuit buffers an input signal received at the routing input from the buffer circuit through a first conductor to generate an output signal that is provided to an input of the receiving circuit through a second conductor only in response to an enable signal at the enable input enabling the programmable repeater circuit.

Abstract: A computer system receives a request to access a server. The request includes a first device tag set. When the first device tag set matches a previously assigned device tag set, the computer system allows access to the server without requesting full access credentials of a user. The computer system invalidates the first device tag set, and sends a second device tag set. When the first device tag set does not match the previously assigned device tag set, the computer system requests full access credentials from the user.

Abstract: A computer-implemented method of determining a discount for purchased items, the method comprising providing a plurality of items to be purchased by a customer, applying a recursive discount scheme for determining available discounts for said plurality of items to be purchased, selecting a highest discount value from said available discounts for said plurality of items, and notifying said customer of said highest discount value for said plurality of items.

Abstract: Integrated circuits are provided that have volatile memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable core logic including transistors with gates. The core logic is powered using a core logic power supply level defined by a core logic positive power supply voltage and a core logic ground voltage. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the core logic to customize the programmable logic device. The memory elements are powered with a memory element power supply level defined by a memory element positive power supply voltage and a memory element ground power supply voltage. The memory element power supply level is elevated with respect to the core logic power supply level.

Abstract: Integrated circuits are provided that have memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable logic including transistors with gates. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the programmable logic device to customize the programmable logic. To ensure that the transistors in the programmable logic are turned on properly, the memory elements are powered with an elevated power supply level during normal device operation. During data loading operations, the power supply level for the memory elements is reduced. Reducing the memory element power supply level during loading increases the write margin for the memory elements.

Abstract: Programmable logic device integrated circuits are provided. The programmable logic device integrated circuits contain programmable core logic powered at a programmable core logic power supply voltage. Programmable logic device configuration data is loaded into the memory elements to configure the programmable core logic to perform a custom logic function. During normal operation the memory elements may be powered with a power supply voltage that is larger than the programmable core logic power supply voltage. During data loading operations, the memory elements may be powered with a power supply voltage equal to the programmable core logic power supply voltage. Data loading and reading circuitry loads data into the memory elements and reads data from the memory elements. Address signals are generated by the data loading and reading circuitry. The address signals may have larger voltage levels during data writing operations than during read operations.

Abstract: An output buffer with feedback to a predriver circuit such that the effective size of the predriver buffers are momentarily adjusted to favor a particular transition (i.e., low-to-high or high-to-low). The delayed output selectively alters the input threshold characteristic of the predriver circuit to favor the appropriate transition. Thus, the time during which the output drivers are subject to a crowbar current is reduced over previous devices.