Abstract: Partially-synchronous and non-integer integrated circuit counters for dividing a high-speed reference clock signal with a selectable divisor have been provided. The circuits use a high-speed synchronous counter that cycles between the use of a selectable and a fixed divisor, to give the counter circuit a selectable overall division ratio. The partially-synchronous counter circuit uses asynchronous dividers to complete the division process and to minimize power consumption. A non-integer counter circuit is provided that includes a edge select mechanism to reduce power consumption in the division process. Examples are presented with specific number of stages, and corresponding divisors and divisor ranges. Method for implementing the above-mentioned partially-synchronous and non-integer counter circuits have also been provided.