Patents by Inventor Mark Cichanowski

Mark Cichanowski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240086608
    Abstract: Embodiments include exerciser device placement in the development of an integrated circuit. Aspects of the invention include obtaining a design of an integrated circuit and creating a dynamic power blockage map for the integrated circuit. Aspects also include updating the integrated circuit design by placing one or more exercisers on the integrated circuit, wherein a location of the one or more exercisers on the integrated circuit is based on at least in part on the dynamic power blockage map. Based on a determination that the updated integrated circuit design complies with one or more design constraints, aspects further include outputting the updated integrated circuit design.
    Type: Application
    Filed: September 8, 2022
    Publication date: March 14, 2024
    Inventors: Michael Romain, Lucas Dane LaLima, Michael Greene, Alper Buyuktosunoglu, Christopher Joseph Berry, Pawel Owczarczyk, Mark Cichanowski, William V. Huott, OFER GEVA, Jesse Peter Surprise, Eduard Herkel
  • Patent number: 11817697
    Abstract: The method and systems described herein provide for identifying and mitigating undesirable power or voltage fluctuations in regions of a semiconductor device. For example, embodiments include detecting a region, such as an individual processor, of a processor chip is exhibiting a reduced power draw and a resulting localized voltage spike (e.g., a spike that exceeds Vmax) that would accelerate overall device end-of-life (EOL). The described systems respond by activating circuits or current generators located in the given region to draw additional power via a protective current. The protective current lowers the local voltages spikes back to within some pre-specified range (e.g., below a Vmax). The resulting reduction in the time above Vmax in testing reduces the number of devices that will need to be discarded due to Vmax violations as well as increases the expected reliability and lifespan of the device in operation.
    Type: Grant
    Filed: April 5, 2022
    Date of Patent: November 14, 2023
    Assignee: International Business Machines Corporation
    Inventors: Adam Benjamin Collura, Michael Romain, William V. Huott, Pawel Owczarczyk, Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum, Alper Buyuktosunoglu, Tobias Webel, Michael Joseph Cadigan, Jr., Paul Jacob Logsdon, Sean Michael Carey, Stefan Payer, Karl Evan Smock Anderson, Mark Cichanowski
  • Publication number: 20230318286
    Abstract: The method and systems described herein provide for identifying and mitigating undesirable power or voltage fluctuations in regions of a semiconductor device. For example, embodiments include detecting a region, such as an individual processor, of a processor chip is exhibiting a reduced power draw and a resulting localized voltage spike (e.g., a spike that exceeds Vmax) that would accelerate overall device end-of-life (EOL). The described systems respond by activating circuits or current generators located in the given region to draw additional power via a protective current. The protective current lowers the local voltages spikes back to within some pre-specified range (e.g., below a Vmax). The resulting reduction in the time above Vmax in testing reduces the number of devices that will need to be discarded due to Vmax violations as well as increases the expected reliability and lifespan of the device in operation.
    Type: Application
    Filed: April 5, 2022
    Publication date: October 5, 2023
    Inventors: Adam Benjamin COLLURA, Michael ROMAIN, William V. HUOTT, Pawel OWCZARCZYK, Christian JACOBI, Anthony SAPORITO, Chung-Lung K. SHUM, Alper BUYUKTOSUNOGLU, Tobias WEBEL, Michael Joseph CADIGAN, JR., Paul Jacob LOGSDON, Sean Michael CAREY, Stefan PAYER, Karl Evan Smock ANDERSON, Mark CICHANOWSKI