Abstract: A method and structure are provided for connecting to integrated circuitry. A connectivity cell includes multiple terminals formed within the integrated circuitry. The connectivity cell further includes at least one metal layer connected to at least one of the terminals. A first area is a substantially minimal area including the connectivity cell. A second area is a substantially minimal area including at least a part of each of multiple portions of the integrated circuitry. The portions are connectable to respective ones of the terminals while having a placement flexibility relative to the terminals. This placement flexibility of the portions is substantially equal to a placement flexibility of the second area within the first area.

Abstract: An automated method for optimally ordering macros within a semiconductor chip data-path stack is disclosed. Each stack macro is assumed to have at least one predetermined bus connection with another macro in the stack. The ordering technique is based on minimizing for each macro in the stack the total number of stack macros passed by buses predeterminedly connected to that macro without making connection thereto. In addition, a macro group is formed of any subset of stack macros caught in a repeating loop. Each macro group contains at least two macros of the stack. Once defined, a macro group is treated as a single stack macro and optimization processing continues. Once the optimal location of all macros is identified, then any formed macro group is expanded and the optimal location of each macro within the group itself is identified. Specific details of the method are provided herein.