Patents by Inventor Mark D. Cavaro

Mark D. Cavaro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Synchronous stack bus for fast Ethernet repeater
    Patent number: 7061931
    Abstract: Provided is a synchronous stack bus repeater system for a computer network. The system includes a plurality of stacked repeaters, a stack bus linking the repeaters, and a single clock to which the plurality of repeaters is synchronized. The synchronization of the stack bus eliminates several time-consuming communications required between devices operating with different clocks on an asynchronous bus and makes it possible to satisfy the 46 bit time repeater maximum latency required of a Class II repeater according to the IEEE 802.3 standard.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: June 13, 2006
    Assignee: Cisco Technology, Inc.
    Inventors: Moshe Voloshin, Mark D. Cavaro
  • Synchronous stack bus for fast ethernet repeater
    Patent number: 6850538
    Abstract: Provided is a synchronous stack bus repeater system for a computer network. The system includes a plurality of stacked repeaters, a stack bus linking the repeaters, and a single clock to which the plurality of repeaters is synchronized. The synchronization of the stack bus eliminates several time-consuming communications required between devices operating with different clocks on an asynchronous bus and makes it possible to satisfy the 46 bit time repeater maximum latency required of a Class II repeater according to the IEEE 802.3 standard.
    Type: Grant
    Filed: September 22, 2000
    Date of Patent: February 1, 2005
    Assignee: Cisco Technology, Inc.
    Inventors: Moshe Voloshin, Mark D. Cavaro
  • Synchronous stack bus for fast Ethernet repeater
    Patent number: 6178176
    Abstract: Provided is a synchronous stack bus repeater system for a computer network. The system includes a plurality of stacked repeaters, a stack bus linking the repeaters, and a single clock to which the plurality of repeaters is synchronized. The synchronization of the stack bus eliminates several time-consuming communications required between devices operating with different clocks on an asynchronous bus and makes it possible to satisfy the 46 bit time repeater maximum latency required of a Class II repeater according to the IEEE 802.3 standard.
    Type: Grant
    Filed: November 6, 1997
    Date of Patent: January 23, 2001
    Assignee: Cisco Technology, Inc
    Inventors: Moshe Voloshin, Mark D. Cavaro