Abstract: A modular, polymorphic network interconnecting a plurality of electronically reconfigurable devices via a modular, polymorphic interconnect, to permit a fixed, physical configuration of operating hardware devices to take on a plurality of logically addressable configurations. The modular, polymorphic interconnect further permits allocation and deallocation of selected electronically reconfigurable devices for a particular logically addressable configuration. The modular, polymorphic interconnect additionally permits the logical topology of selected electronically reconfigurable devices to be configured as at least one mixed-radix, N-dimensional network. The logical topology of mixed-radix, N-dimensional networks can be dynamically changed under control for a new configuration of logical addresses for selected electronically reconfigurable devices.

Abstract: A reconfigurable, associative network apparatus and method. During a configuration phase of the associative network apparatus, active signals corresponding to wanted input patterns are configured as an associative network and distinguished from signals corresponding to unwanted input patterns; wanted input patterns can be further associated with output patterns corresponding to wanted responses. During an operational phase of a previously configured associative network, input patterns are formed from signals produced by one or a plurality of activated inputs. Selected input patterns are then filtered from a set of possible input patterns, and output patterns are obtained in response to a particular set of connections between input and output signals.

Abstract: A modular, polymorphic network interconnecting a plurality of electronically reconfigurable devices via a modular, polymorphic interconnect, to permit a fixed, physical configuration of operating hardware devices to take on a plurality of logically addressable configurations. The modular, polymorphic interconnect further permits allocation and deallocation of selected electronically reconfigurable devices for a particular logically addressable configuration. The modular, polymorphic interconnect additionally permits the logical topology of selected electronically reconfigurable devices to be configured as at least one mixed-radix, N-dimensional network. The logical topology of mixed-radix, N-dimensional networks can be dynamically changed under control for a new configuration of logical addresses for selected electronically reconfigurable devices.

Abstract: Object spaces which mechanize higher order relationships between attributes which describe a particular problem domain. An abstract object description defined by a set of attributes and their corresponding values is transformed into a mixed-resolution, N-dimensional object space. The mixed-resolution, N-dimensional object space represents a mechanized, logically encoded expression of attribute relationships that can be visualized. The method and apparatus interleave the frame to generate an object descriptor and generate from the frame and the object descriptor, encoded names of spatial locations for each of the N dimensions of the mixed-resolution, N-dimensional, object space, conforming to a primary form of a reflected binary code. A virtual image of the N-dimensional, object space is generated from the dimensional-spatial locations and resolution-spatial locations, and attribute values corresponding to a region of the virtual image may be selected for display.

Abstract: A chordal keyboard method and apparatus for generating a key code using a plurality of keys coupled to a controller with a first set of registers and a second set of registers. A user depresses at least one of the plurality of keys. The controller detects, which of the plurality of keys are in a depressed position and which of the plurality of keys are released from the depressed position. The controller sets in the first set of registers and sets in the second set of registers, bit locations of respective depressed keys, and clears in the second set of registers bit locations of respective released keys. When the controller detects that all of the plurality of keys are in a released position, a key code is generated which corresponds to bit locations set in the first set of registers. After generating the key code, the controller clears the first set of registers.